diff options
| author | Arun Ramadoss <arun.ramadoss@microchip.com> | 2022-09-02 16:02:10 +0530 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-09-05 13:06:40 +0100 |
| commit | c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8 (patch) | |
| tree | 52b2db4dea639df4013c3005ba63fe1b2fab344a /drivers/net/dsa/microchip/lan937x_reg.h | |
| parent | f313936261ac18a2527fc0752cf988950587d0ce (diff) | |
| download | linux-c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8.tar.gz linux-c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8.tar.bz2 linux-c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8.zip | |
net: dsa: microchip: lan937x: add interrupt support for port phy link
This patch enables the interrupts for internal phy link detection for
LAN937x. The interrupt enable bits are active low. There is global
interrupt mask for each port. And each port has the individual interrupt
mask for TAS. QCI, SGMII, PTP, PHY and ACL.
The first level of interrupt domain is registered for global port
interrupt and second level of interrupt domain for the individual port
interrupts. The phy interrupt is enabled in the lan937x_mdio_register
function. Interrupt from which port is raised will be detected based on
the interrupt host data.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/microchip/lan937x_reg.h')
| -rw-r--r-- | drivers/net/dsa/microchip/lan937x_reg.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index ba4adaddb3ec..a3c669d86e51 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -118,6 +118,18 @@ /* Port Registers */ /* 0 - Operation */ +#define REG_PORT_INT_STATUS 0x001B +#define REG_PORT_INT_MASK 0x001F + +#define PORT_TAS_INT BIT(5) +#define PORT_QCI_INT BIT(4) +#define PORT_SGMII_INT BIT(3) +#define PORT_PTP_INT BIT(2) +#define PORT_PHY_INT BIT(1) +#define PORT_ACL_INT BIT(0) + +#define PORT_SRC_PHY_INT 1 + #define REG_PORT_CTRL_0 0x0020 #define PORT_MAC_LOOPBACK BIT(7) |