diff options
| author | Vinicius Costa Gomes <vinicius.gomes@intel.com> | 2020-02-14 15:52:02 -0800 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2020-04-17 10:19:24 -0700 |
| commit | ec50a9d437f05dd76444a65fdd3cfbfad90ee9d6 (patch) | |
| tree | 4962301811790846c2a5c25474837418b87a8a4a /drivers/net/ethernet/intel/igc/igc_regs.h | |
| parent | 34428dff3679f0c4c9b185ff8eccefd12a7f55f8 (diff) | |
| download | linux-ec50a9d437f05dd76444a65fdd3cfbfad90ee9d6.tar.gz linux-ec50a9d437f05dd76444a65fdd3cfbfad90ee9d6.tar.bz2 linux-ec50a9d437f05dd76444a65fdd3cfbfad90ee9d6.zip | |
igc: Add support for taprio offloading
Adds support for translating taprio schedules into i225 cycles. This
will allow schedules to run in the hardware, making the schedules
enforcement more precise and saving CPU time.
Right now, the only simple schedules are allowed, complex schedules are
rejected. "simple" in this context are schedules that each HW queue is
opened and closed only once in each cycle.
Changing schedules is still not supported as well.
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Reviewed-by: Andre Guedes <andre.guedes@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/igc/igc_regs.h')
| -rw-r--r-- | drivers/net/ethernet/intel/igc/igc_regs.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h index d4af53a80f11..6093cde2351c 100644 --- a/drivers/net/ethernet/intel/igc/igc_regs.h +++ b/drivers/net/ethernet/intel/igc/igc_regs.h @@ -231,6 +231,18 @@ #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ +/* Transmit Scheduling Registers */ +#define IGC_TQAVCTRL 0x3570 +#define IGC_TXQCTL(_n) (0x3344 + 0x4 * (_n)) +#define IGC_BASET_L 0x3314 +#define IGC_BASET_H 0x3318 +#define IGC_QBVCYCLET 0x331C +#define IGC_QBVCYCLET_S 0x3320 + +#define IGC_STQT(_n) (0x3324 + 0x4 * (_n)) +#define IGC_ENDQT(_n) (0x3334 + 0x4 * (_n)) +#define IGC_DTXMXPKTSZ 0x355C + /* System Time Registers */ #define IGC_SYSTIML 0x0B600 /* System time register Low - RO */ #define IGC_SYSTIMH 0x0B604 /* System time register High - RO */ |