Merge branch 'remotes/lorenzo/pci/dwc'

- Fix designware-ep Header Type check (Hou Zhiqiang)

- Use DBI accessors instead of own config accessors (Rob Herring)

- Allow overriding bridge pci_ops (Rob Herring)

- Allow root and child buses to have different pci_ops (Rob Herring)

- Add default dwc pci_ops.map_bus (Rob Herring)

- Use pci_ops for root config space accessors in al, exynos, histb,
  keystone, kirin, meson, tegra (Rob Herring)

- Remove dwc own/other config accessor ops (Rob Herring)

- Use generic config accessors in dwc (Rob Herring)

- Also call .add_bus() callback for root bus (Rob Herring)

- Convert keystone .scan_bus() callback to use pci_ops.add_bus (Rob
  Herring)

- Convert dwc to use pci_host_probe() (Rob Herring)

- Remove dwc root_bus pointer (Rob Herring)

- Remove storing of PCI resources in dwc-specific structs (Rob Herring)

- Simplify config space handling (Rob Herring)

- Drop keystone duplicated DT num-viewport handling (Rob Herring)

- Check CONFIG_PCI_MSI in dw_pcie_msi_init() instead of duplicating it in
  all the drivers (Rob Herring)

- Remove imx6 duplicate PCIE_LINK_WIDTH_SPEED_CONTROL definition (Rob
  Herring)

- Add dwc num_lanes for use when it's lacking from DT (Rob Herring)

- Ensure "Fast Link Mode" simulation environment setting is cleared (Rob
  Herring)

- Drop meson duplicate number of lanes setup (Rob Herring)

- Drop meson unnecessary RC config space init (Rob Herring)

- Rework meson config and dwc port logic register accesses (Rob Herring)

- Use common PCI register definitions in imx6 and qcom (Rob Herring)

- Search for DesignWare PCIe Capability instead of hard-coding its location
  (Rob Herring)

- Use common DesignWare register definitions in tegra (Rob Herring)

- Drop keystone unused DBI2 code (Rob Herring)

- Make dwc ATU accessors private (Rob Herring)

- Centralize link gen setting in dwc (Rob Herring)

- Set PORT_LINK_DLL_LINK_EN in common dwc setup code (Rob Herring)

- Drop intel-gw unnecessary DT 'device_type' checking (Rob Herring)

- Move intel-gw PCI_CAP_ID_EXP discovery to the single place it's used (Rob
  Herring)

- Drop intel-gw unused max_width (Rob Herring)

- Move N_FTS (fast training sequence) setup to common dwc setup (Rob
  Herring)

- Convert spear13xx, tegra194 to use DBI accessors (Rob Herring)

- Add multiple PFs support for DWC (Xiaowei Bao)

- Add MSI-X doorbell mode for endpoint mode (Xiaowei Bao)

- Update MSI/MSI-X capability management for endpoints (Xiaowei Bao)

- Add layerscape ls1088a and ls2088a compatible strings (Xiaowei Bao)

- Update layerscape MSI/MSI-X management (Xiaowei Bao)

- Use doorbell to support MSI-X on layerscape (Xiaowei Bao)

- Add layerscape endpoint mode support for ls1088a and ls2088a (Xiaowei
  Bao)

- Add layerscape ls1088a node to DT (Xiaowei Bao)

- Add Freescale/Layerscape ls1088a to endpoint test (Xiaowei Bao)

- Add endpoint test driver data for Layerscape PCIe controllers (Hou
  Zhiqiang)

- Fix 'cast truncates bits from constant value' warning (Gustavo Pimentel)

- Add uniphier iATU register description (Kunihiko Hayashi)

- Add common iATU register support (Kunihiko Hayashi)

- Remove keystone iATU register mapping in favor of generic dwc support
  (Kunihiko Hayashi)

- Skip PCIE_MSI_INTR0* programming if MSI is disabled (Jisheng Zhang)

- Fix MSI page leakage in suspend/resume (Jisheng Zhang)

- Check whether link is up before attempting config access (best-effort fix
  even though it's racy) (Hou Zhiqiang)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus()
  PCI: dwc: Fix MSI page leakage in suspend/resume
  PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled
  PCI: keystone: Remove iATU register mapping
  PCI: dwc: Add common iATU register support
  dt-bindings: PCI: uniphier-ep: Add iATU register description
  dt-bindings: PCI: uniphier: Add iATU register description
  PCI: dwc: Fix 'cast truncates bits from constant value'
  misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllers
  misc: pci_endpoint_test: Add LS1088a in pci_device_id table
  PCI: layerscape: Add EP mode support for ls1088a and ls2088a
  PCI: layerscape: Modify the MSIX to the doorbell mode
  PCI: layerscape: Modify the way of getting capability with different PEX
  PCI: layerscape: Fix some format issue of the code
  dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a
  PCI: designware-ep: Modify MSI and MSIX CAP way of finding
  PCI: designware-ep: Move the function of getting MSI capability forward
  PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode
  PCI: designware-ep: Add multiple PFs support for DWC
  PCI: dwc: Use DBI accessors
  PCI: dwc: Move N_FTS setup to common setup
  PCI: dwc/intel-gw: Drop unused max_width
  PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()
  PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property
  PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code
  PCI: dwc: Centralize link gen setting
  PCI: dwc: Make ATU accessors private
  PCI: dwc: Remove read_dbi2 code
  PCI: dwc/tegra: Use common Designware port logic register definitions
  PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset
  PCI: dwc/qcom: Use common PCI register definitions
  PCI: dwc/imx6: Use common PCI register definitions
  PCI: dwc/meson: Rework PCI config and DW port logic register accesses
  PCI: dwc/meson: Drop unnecessary RC config space initialization
  PCI: dwc/meson: Drop the duplicate number of lanes setup
  PCI: dwc: Ensure FAST_LINK_MODE is cleared
  PCI: dwc: Add a 'num_lanes' field to struct dw_pcie
  PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL
  PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()
  PCI: dwc/keystone: Drop duplicated 'num-viewport'
  PCI: dwc: Simplify config space handling
  PCI: dwc: Remove storing of PCI resources
  PCI: dwc: Remove root_bus pointer
  PCI: dwc: Convert to use pci_host_probe()
  PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus
  PCI: Also call .add_bus() callback for root bus
  PCI: dwc: Use generic config accessors
  PCI: dwc: Remove dwc specific config accessor ops
  PCI: dwc: histb: Use pci_ops for root config space accessors
  PCI: dwc: exynos: Use pci_ops for root config space accessors
  PCI: dwc: kirin: Use pci_ops for root config space accessors
  PCI: dwc: meson: Use pci_ops for root config space accessors
  PCI: dwc: tegra: Use pci_ops for root config space accessors
  PCI: dwc: keystone: Use pci_ops for config space accessors
  PCI: dwc: al: Use pci_ops for child config space accessors
  PCI: dwc: Add a default pci_ops.map_bus for root port
  PCI: dwc: Allow overriding bridge pci_ops
  PCI: dwc: Use DBI accessors instead of own config accessors
  PCI: Allow root and child buses to have different pci_ops
  PCI: designware-ep: Fix the Header Type check

1 files changed, 6 insertions, 33 deletions

diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c
index 62846562da0b..e348225f651f 100644
--- a/drivers/pci/controller/dwc/pcie-spear13xx.c
+++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
@@ -26,7 +26,6 @@ struct spear13xx_pcie {
 	void __iomem		*app_base;
 	struct phy		*phy;
 	struct clk		*clk;
-	bool			is_gen1;
 };
 
 struct pcie_app_reg {
@@ -65,8 +64,6 @@ struct pcie_app_reg {
 /* CR6 */
 #define MSI_CTRL_INT				(1 << 26)
 
-#define EXP_CAP_ID_OFFSET			0x70
-
 #define to_spear13xx_pcie(x)	dev_get_drvdata((x)->dev)
 
 static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
@@ -75,7 +72,7 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
 	struct pcie_port *pp = &pci->pp;
 	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
 	u32 val;
-	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
+	u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 
 	if (dw_pcie_link_up(pci)) {
 		dev_err(pci->dev, "link already up\n");
@@ -89,36 +86,12 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
 	 * default value in capability register is 512 bytes. So force
 	 * it to 128 here.
 	 */
-	dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
+	val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL);
 	val &= ~PCI_EXP_DEVCTL_READRQ;
-	dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
-
-	dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
-	dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
+	dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val);
 
-	/*
-	 * if is_gen1 is set then handle it, so that some buggy card
-	 * also works
-	 */
-	if (spear13xx_pcie->is_gen1) {
-		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
-			     4, &val);
-		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
-			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
-			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
-			dw_pcie_write(pci->dbi_base + exp_cap_off +
-				      PCI_EXP_LNKCAP, 4, val);
-		}
-
-		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
-			     2, &val);
-		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
-			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
-			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
-			dw_pcie_write(pci->dbi_base + exp_cap_off +
-				      PCI_EXP_LNKCTL2, 2, val);
-		}
-	}
+	dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A);
+	dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80);
 
 	/* enable ltssm */
 	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
@@ -278,7 +251,7 @@ static int spear13xx_pcie_probe(struct platform_device *pdev)
 	spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
 
 	if (of_property_read_bool(np, "st,pcie-is-gen1"))
-		spear13xx_pcie->is_gen1 = true;
+		pci->link_gen = 1;
 
 	platform_set_drvdata(pdev, spear13xx_pcie);