Merge branch 'pci/controller/kconfig'

- Use uniform language in Kconfig menu entries (Bjorn Helgaas)

- Sort controller Kconfig entries by vendor (Bjorn Helgaas)

* pci/controller/kconfig:
  PCI: xilinx: Drop obsolete dependency on COMPILE_TEST
  PCI: mobiveil: Sort Kconfig entries by vendor
  PCI: dwc: Sort Kconfig entries by vendor
  PCI: Sort controller Kconfig entries by vendor
  PCI: Use consistent controller Kconfig menu entry language
  PCI: xilinx-nwl: Add 'Xilinx' to Kconfig prompt
  PCI: hv: Add 'Microsoft' to Kconfig prompt
  PCI: meson: Add 'Amlogic' to Kconfig prompt
  PCI: Use of_property_present() for testing DT property presence
  PCI/PM: Extend D3hot delay for NVIDIA HDA controllers
  dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties
  PCI: qcom: Add SM8550 PCIe support
  dt-bindings: PCI: qcom: Add SM8550 compatible
  PCI: qcom: Add support for SDX55 SoC
  dt-bindings: PCI: qcom-ep: Fix the unit address used in example
  dt-bindings: PCI: qcom: Add SDX55 SoC
  dt-bindings: PCI: qcom: Update maintainers entry
  PCI: qcom: Enable async probe by default
  PCI: qcom: Add support for system suspend and resume
  PCI/PM: Drop pci_bridge_wait_for_secondary_bus() timeout parameter
  PCI/PM: Increase wait time after resume
  PCI: pciehp: Fix AB-BA deadlock between reset_lock and device_lock
  PCI: Fix up L1SS capability for Intel Apollo Lake Root Port
  PCI: qcom: Expose link transition counts via debugfs
  dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs
  PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version
  PCI: qcom: Use macros for defining total no. of clocks & supplies
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0
  PCI: qcom: Use lower case for hex
  PCI: qcom: Add missing macros for register fields
  PCI: qcom: Use bitfield definitions for register fields
  PCI: qcom: Sort and group registers and bitfield definitions
  PCI: qcom: Remove PCIE20_ prefix from register definitions
  PCI: qcom: Fix the incorrect register usage in v2.7.0 config
  PCI/EDR: Add edr_handle_event() comments
  PCI/EDR: Clear Device Status after EDR error recovery
  efi/cper: Remove unnecessary aer.h include
  dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema
  PCI/P2PDMA: Fix pci_p2pmem_find_many() kernel-doc
  EISA: Drop unused pci_bus_for_each_resource() index argument
  PCI: Make pci_bus_for_each_resource() index optional
  PCI: Document pci_bus_for_each_resource()
  PCI: Introduce pci_dev_for_each_resource()
  PCI: Introduce pci_resource_n()
  PCI: ixp4xx: Use PCI_CONF1_ADDRESS() macro
  PCI: mt7621: Use dev_info() to log PCIe card detection
  PCI: imx6: Install the fault handler only on compatible match
  PCI: layerscape: Add EP mode support for ls1028a
  PCI: rcar: Avoid defines prefixed with CONFIG
  dt-bindings: PCI: convert amlogic,meson-pcie.txt to dt-schema
  PCI: kirin: Select REGMAP_MMIO

1 files changed, 13 insertions, 8 deletions

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7a67611dc5f4..199024beaee9 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -64,6 +64,14 @@ struct pci_pme_device {
 
 #define PME_TIMEOUT 1000 /* How long between PME checks */
 
+/*
+ * Devices may extend the 1 sec period through Request Retry Status
+ * completions (PCIe r6.0 sec 2.3.1).  The spec does not provide an upper
+ * limit, but 60 sec ought to be enough for any device to become
+ * responsive.
+ */
+#define PCIE_RESET_READY_POLL_MS 60000 /* msec */
+
 static void pci_dev_d3_sleep(struct pci_dev *dev)
 {
 	unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
@@ -779,9 +787,8 @@ struct resource *pci_find_parent_resource(const struct pci_dev *dev,
 {
 	const struct pci_bus *bus = dev->bus;
 	struct resource *r;
-	int i;
 
-	pci_bus_for_each_resource(bus, r, i) {
+	pci_bus_for_each_resource(bus, r) {
 		if (!r)
 			continue;
 		if (resource_contains(r, res)) {
@@ -4939,7 +4946,6 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
  * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
  * @dev: PCI bridge
  * @reset_type: reset type in human-readable form
- * @timeout: maximum time to wait for devices on secondary bus (milliseconds)
  *
  * Handle necessary delays before access to the devices on the secondary
  * side of the bridge are permitted after D3cold to D0 transition
@@ -4952,8 +4958,7 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
  * Return 0 on success or -ENOTTY if the first device on the secondary bus
  * failed to become accessible.
  */
-int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
-				      int timeout)
+int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
 {
 	struct pci_dev *child;
 	int delay;
@@ -5031,7 +5036,8 @@ int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
 		}
 	}
 
-	return pci_dev_wait(child, reset_type, timeout - delay);
+	return pci_dev_wait(child, reset_type,
+			    PCIE_RESET_READY_POLL_MS - delay);
 }
 
 void pci_reset_secondary_bus(struct pci_dev *dev)
@@ -5068,8 +5074,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
 {
 	pcibios_reset_secondary_bus(dev);
 
-	return pci_bridge_wait_for_secondary_bus(dev, "bus reset",
-						 PCIE_RESET_READY_POLL_MS);
+	return pci_bridge_wait_for_secondary_bus(dev, "bus reset");
 }
 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);