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authorJithu Joseph <jithu.joseph@intel.com>2023-03-21 17:33:55 -0700
committerHans de Goede <hdegoede@redhat.com>2023-03-27 16:10:20 +0200
commitd31bbdf42b46cb8dc81deb48c4bf5234dd63d939 (patch)
tree0820b32d96501d98d78f0bcbceef3c341dcb6c55 /drivers/platform/x86/intel/ifs/core.c
parentc68e3d473988b9af1f39355be57befb83607d845 (diff)
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platform/x86/intel/ifs: Introduce Array Scan test to IFS
Array BIST is a new type of core test introduced under the Intel Infield Scan (IFS) suite of tests. Emerald Rapids (EMR) is the first CPU to support Array BIST. Array BIST performs tests on some portions of the core logic such as caches and register files. These are different portions of the silicon compared to the parts tested by the first test type i.e Scan at Field (SAF). Make changes in the device driver init flow to register this new test type with the device driver framework. Each test will have its own sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to accommodate for the differences in test type and how they are initiated. Upcoming patches will add actual support. Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20230322003359.213046-6-jithu.joseph@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform/x86/intel/ifs/core.c')
-rw-r--r--drivers/platform/x86/intel/ifs/core.c65
1 files changed, 47 insertions, 18 deletions
diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/intel/ifs/core.c
index f272644617a3..0067eee25f3c 100644
--- a/drivers/platform/x86/intel/ifs/core.c
+++ b/drivers/platform/x86/intel/ifs/core.c
@@ -16,6 +16,7 @@
static const struct x86_cpu_id ifs_cpu_ids[] __initconst = {
X86_MATCH(SAPPHIRERAPIDS_X),
+ X86_MATCH(EMERALDRAPIDS_X),
{}
};
MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids);
@@ -26,23 +27,50 @@ bool *ifs_pkg_auth;
static const struct ifs_test_caps scan_test = {
.integrity_cap_bit = MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT,
- .test_num = 0,
+ .test_num = IFS_TYPE_SAF,
};
-static struct ifs_device ifs_device = {
- .test_caps = &scan_test,
- .misc = {
- .name = "intel_ifs_0",
- .minor = MISC_DYNAMIC_MINOR,
- .groups = plat_ifs_groups,
+static const struct ifs_test_caps array_test = {
+ .integrity_cap_bit = MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT,
+ .test_num = IFS_TYPE_ARRAY_BIST,
+};
+
+static struct ifs_device ifs_devices[] = {
+ [IFS_TYPE_SAF] = {
+ .test_caps = &scan_test,
+ .misc = {
+ .name = "intel_ifs_0",
+ .minor = MISC_DYNAMIC_MINOR,
+ .groups = plat_ifs_groups,
+ },
+ },
+ [IFS_TYPE_ARRAY_BIST] = {
+ .test_caps = &array_test,
+ .misc = {
+ .name = "intel_ifs_1",
+ .minor = MISC_DYNAMIC_MINOR,
+ },
},
};
+#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices)
+
+static void ifs_cleanup(void)
+{
+ int i;
+
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (ifs_devices[i].misc.this_device)
+ misc_deregister(&ifs_devices[i].misc);
+ }
+ kfree(ifs_pkg_auth);
+}
+
static int __init ifs_init(void)
{
const struct x86_cpu_id *m;
u64 msrval;
- int ret;
+ int i, ret;
m = x86_match_cpu(ifs_cpu_ids);
if (!m)
@@ -57,26 +85,27 @@ static int __init ifs_init(void)
if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval))
return -ENODEV;
- if (!(msrval & BIT(ifs_device.test_caps->integrity_cap_bit)))
- return -ENODEV;
-
ifs_pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);
if (!ifs_pkg_auth)
return -ENOMEM;
- ret = misc_register(&ifs_device.misc);
- if (ret) {
- kfree(ifs_pkg_auth);
- return ret;
+ for (i = 0; i < IFS_NUMTESTS; i++) {
+ if (!(msrval & BIT(ifs_devices[i].test_caps->integrity_cap_bit)))
+ continue;
+ ret = misc_register(&ifs_devices[i].misc);
+ if (ret)
+ goto err_exit;
}
-
return 0;
+
+err_exit:
+ ifs_cleanup();
+ return ret;
}
static void __exit ifs_exit(void)
{
- misc_deregister(&ifs_device.misc);
- kfree(ifs_pkg_auth);
+ ifs_cleanup();
}
module_init(ifs_init);