soc: imx: Move power-domain drivers to the genpd dir

To simplify with maintenance let's move the imx power-domain drivers to the
new genpd directory. Going forward, patches are intended to be managed
through a separate git tree, according to MAINTAINERS.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: <kernel@pengutronix.de>
Cc: <linux-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

7 files changed, 1 insertions, 4487 deletions

diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index a28c44a1f16a..3ad321ca608a 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -2,10 +2,5 @@
 ifeq ($(CONFIG_ARM),y)
 obj-$(CONFIG_ARCH_MXC) += soc-imx.o
 endif
-obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
-obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
 obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
-obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8m-blk-ctrl.o
-obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8mp-blk-ctrl.o
-obj-$(CONFIG_SOC_IMX9) += imx93-src.o imx93-pd.o
-obj-$(CONFIG_IMX9_BLK_CTRL) += imx93-blk-ctrl.o
+obj-$(CONFIG_SOC_IMX9) += imx93-src.o
diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c
deleted file mode 100644
index 90a8b2c0676f..000000000000
--- a/drivers/soc/imx/gpc.c
+++ /dev/null
@@ -1,554 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
-#include <linux/regmap.h>
-#include <linux/regulator/consumer.h>
-
-#define GPC_CNTR		0x000
-
-#define GPC_PGC_CTRL_OFFS	0x0
-#define GPC_PGC_PUPSCR_OFFS	0x4
-#define GPC_PGC_PDNSCR_OFFS	0x8
-#define GPC_PGC_SW2ISO_SHIFT	0x8
-#define GPC_PGC_SW_SHIFT	0x0
-
-#define GPC_PGC_PCI_PDN		0x200
-#define GPC_PGC_PCI_SR		0x20c
-
-#define GPC_PGC_GPU_PDN		0x260
-#define GPC_PGC_GPU_PUPSCR	0x264
-#define GPC_PGC_GPU_PDNSCR	0x268
-#define GPC_PGC_GPU_SR		0x26c
-
-#define GPC_PGC_DISP_PDN	0x240
-#define GPC_PGC_DISP_SR		0x24c
-
-#define GPU_VPU_PUP_REQ		BIT(1)
-#define GPU_VPU_PDN_REQ		BIT(0)
-
-#define GPC_CLK_MAX		7
-
-#define PGC_DOMAIN_FLAG_NO_PD		BIT(0)
-
-struct imx_pm_domain {
-	struct generic_pm_domain base;
-	struct regmap *regmap;
-	struct regulator *supply;
-	struct clk *clk[GPC_CLK_MAX];
-	int num_clks;
-	unsigned int reg_offs;
-	signed char cntr_pdn_bit;
-	unsigned int ipg_rate_mhz;
-};
-
-static inline struct imx_pm_domain *
-to_imx_pm_domain(struct generic_pm_domain *genpd)
-{
-	return container_of(genpd, struct imx_pm_domain, base);
-}
-
-static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
-{
-	struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
-	int iso, iso2sw;
-	u32 val;
-
-	/* Read ISO and ISO2SW power down delays */
-	regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PDNSCR_OFFS, &val);
-	iso = val & 0x3f;
-	iso2sw = (val >> 8) & 0x3f;
-
-	/* Gate off domain when powered down */
-	regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
-			   0x1, 0x1);
-
-	/* Request GPC to power down domain */
-	val = BIT(pd->cntr_pdn_bit);
-	regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
-
-	/* Wait ISO + ISO2SW IPG clock cycles */
-	udelay(DIV_ROUND_UP(iso + iso2sw, pd->ipg_rate_mhz));
-
-	if (pd->supply)
-		regulator_disable(pd->supply);
-
-	return 0;
-}
-
-static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
-{
-	struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
-	int i, ret;
-	u32 val, req;
-
-	if (pd->supply) {
-		ret = regulator_enable(pd->supply);
-		if (ret) {
-			pr_err("%s: failed to enable regulator: %d\n",
-			       __func__, ret);
-			return ret;
-		}
-	}
-
-	/* Enable reset clocks for all devices in the domain */
-	for (i = 0; i < pd->num_clks; i++)
-		clk_prepare_enable(pd->clk[i]);
-
-	/* Gate off domain when powered down */
-	regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
-			   0x1, 0x1);
-
-	/* Request GPC to power up domain */
-	req = BIT(pd->cntr_pdn_bit + 1);
-	regmap_update_bits(pd->regmap, GPC_CNTR, req, req);
-
-	/* Wait for the PGC to handle the request */
-	ret = regmap_read_poll_timeout(pd->regmap, GPC_CNTR, val, !(val & req),
-				       1, 50);
-	if (ret)
-		pr_err("powerup request on domain %s timed out\n", genpd->name);
-
-	/* Wait for reset to propagate through peripherals */
-	usleep_range(5, 10);
-
-	/* Disable reset clocks for all devices in the domain */
-	for (i = 0; i < pd->num_clks; i++)
-		clk_disable_unprepare(pd->clk[i]);
-
-	return 0;
-}
-
-static int imx_pgc_get_clocks(struct device *dev, struct imx_pm_domain *domain)
-{
-	int i, ret;
-
-	for (i = 0; ; i++) {
-		struct clk *clk = of_clk_get(dev->of_node, i);
-		if (IS_ERR(clk))
-			break;
-		if (i >= GPC_CLK_MAX) {
-			dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
-			ret = -EINVAL;
-			goto clk_err;
-		}
-		domain->clk[i] = clk;
-	}
-	domain->num_clks = i;
-
-	return 0;
-
-clk_err:
-	while (i--)
-		clk_put(domain->clk[i]);
-
-	return ret;
-}
-
-static void imx_pgc_put_clocks(struct imx_pm_domain *domain)
-{
-	int i;
-
-	for (i = domain->num_clks - 1; i >= 0; i--)
-		clk_put(domain->clk[i]);
-}
-
-static int imx_pgc_parse_dt(struct device *dev, struct imx_pm_domain *domain)
-{
-	/* try to get the domain supply regulator */
-	domain->supply = devm_regulator_get_optional(dev, "power");
-	if (IS_ERR(domain->supply)) {
-		if (PTR_ERR(domain->supply) == -ENODEV)
-			domain->supply = NULL;
-		else
-			return PTR_ERR(domain->supply);
-	}
-
-	/* try to get all clocks needed for reset propagation */
-	return imx_pgc_get_clocks(dev, domain);
-}
-
-static int imx_pgc_power_domain_probe(struct platform_device *pdev)
-{
-	struct imx_pm_domain *domain = pdev->dev.platform_data;
-	struct device *dev = &pdev->dev;
-	int ret;
-
-	/* if this PD is associated with a DT node try to parse it */
-	if (dev->of_node) {
-		ret = imx_pgc_parse_dt(dev, domain);
-		if (ret)
-			return ret;
-	}
-
-	/* initially power on the domain */
-	if (domain->base.power_on)
-		domain->base.power_on(&domain->base);
-
-	if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
-		pm_genpd_init(&domain->base, NULL, false);
-		ret = of_genpd_add_provider_simple(dev->of_node, &domain->base);
-		if (ret)
-			goto genpd_err;
-	}
-
-	device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE_CONSUMER);
-
-	return 0;
-
-genpd_err:
-	pm_genpd_remove(&domain->base);
-	imx_pgc_put_clocks(domain);
-
-	return ret;
-}
-
-static int imx_pgc_power_domain_remove(struct platform_device *pdev)
-{
-	struct imx_pm_domain *domain = pdev->dev.platform_data;
-
-	if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
-		of_genpd_del_provider(pdev->dev.of_node);
-		pm_genpd_remove(&domain->base);
-		imx_pgc_put_clocks(domain);
-	}
-
-	return 0;
-}
-
-static const struct platform_device_id imx_pgc_power_domain_id[] = {
-	{ "imx-pgc-power-domain"},
-	{ },
-};
-
-static struct platform_driver imx_pgc_power_domain_driver = {
-	.driver = {
-		.name = "imx-pgc-pd",
-	},
-	.probe = imx_pgc_power_domain_probe,
-	.remove = imx_pgc_power_domain_remove,
-	.id_table = imx_pgc_power_domain_id,
-};
-builtin_platform_driver(imx_pgc_power_domain_driver)
-
-#define GPC_PGC_DOMAIN_ARM	0
-#define GPC_PGC_DOMAIN_PU	1
-#define GPC_PGC_DOMAIN_DISPLAY	2
-#define GPC_PGC_DOMAIN_PCI	3
-
-static struct genpd_power_state imx6_pm_domain_pu_state = {
-	.power_off_latency_ns = 25000,
-	.power_on_latency_ns = 2000000,
-};
-
-static struct imx_pm_domain imx_gpc_domains[] = {
-	[GPC_PGC_DOMAIN_ARM] = {
-		.base = {
-			.name = "ARM",
-			.flags = GENPD_FLAG_ALWAYS_ON,
-		},
-	},
-	[GPC_PGC_DOMAIN_PU] = {
-		.base = {
-			.name = "PU",
-			.power_off = imx6_pm_domain_power_off,
-			.power_on = imx6_pm_domain_power_on,
-			.states = &imx6_pm_domain_pu_state,
-			.state_count = 1,
-		},
-		.reg_offs = 0x260,
-		.cntr_pdn_bit = 0,
-	},
-	[GPC_PGC_DOMAIN_DISPLAY] = {
-		.base = {
-			.name = "DISPLAY",
-			.power_off = imx6_pm_domain_power_off,
-			.power_on = imx6_pm_domain_power_on,
-		},
-		.reg_offs = 0x240,
-		.cntr_pdn_bit = 4,
-	},
-	[GPC_PGC_DOMAIN_PCI] = {
-		.base = {
-			.name = "PCI",
-			.power_off = imx6_pm_domain_power_off,
-			.power_on = imx6_pm_domain_power_on,
-		},
-		.reg_offs = 0x200,
-		.cntr_pdn_bit = 6,
-	},
-};
-
-struct imx_gpc_dt_data {
-	int num_domains;
-	bool err009619_present;
-	bool err006287_present;
-};
-
-static const struct imx_gpc_dt_data imx6q_dt_data = {
-	.num_domains = 2,
-	.err009619_present = false,
-	.err006287_present = false,
-};
-
-static const struct imx_gpc_dt_data imx6qp_dt_data = {
-	.num_domains = 2,
-	.err009619_present = true,
-	.err006287_present = false,
-};
-
-static const struct imx_gpc_dt_data imx6sl_dt_data = {
-	.num_domains = 3,
-	.err009619_present = false,
-	.err006287_present = true,
-};
-
-static const struct imx_gpc_dt_data imx6sx_dt_data = {
-	.num_domains = 4,
-	.err009619_present = false,
-	.err006287_present = false,
-};
-
-static const struct of_device_id imx_gpc_dt_ids[] = {
-	{ .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
-	{ .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
-	{ .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
-	{ .compatible = "fsl,imx6sx-gpc", .data = &imx6sx_dt_data },
-	{ }
-};
-
-static const struct regmap_range yes_ranges[] = {
-	regmap_reg_range(GPC_CNTR, GPC_CNTR),
-	regmap_reg_range(GPC_PGC_PCI_PDN, GPC_PGC_PCI_SR),
-	regmap_reg_range(GPC_PGC_GPU_PDN, GPC_PGC_GPU_SR),
-	regmap_reg_range(GPC_PGC_DISP_PDN, GPC_PGC_DISP_SR),
-};
-
-static const struct regmap_access_table access_table = {
-	.yes_ranges	= yes_ranges,
-	.n_yes_ranges	= ARRAY_SIZE(yes_ranges),
-};
-
-static const struct regmap_config imx_gpc_regmap_config = {
-	.reg_bits = 32,
-	.val_bits = 32,
-	.reg_stride = 4,
-	.rd_table = &access_table,
-	.wr_table = &access_table,
-	.max_register = 0x2ac,
-	.fast_io = true,
-};
-
-static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
-	&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base,
-	&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base,
-};
-
-static struct genpd_onecell_data imx_gpc_onecell_data = {
-	.domains = imx_gpc_onecell_domains,
-	.num_domains = 2,
-};
-
-static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap,
-			       unsigned int num_domains)
-{
-	struct imx_pm_domain *domain;
-	int i, ret;
-
-	for (i = 0; i < num_domains; i++) {
-		domain = &imx_gpc_domains[i];
-		domain->regmap = regmap;
-		domain->ipg_rate_mhz = 66;
-
-		if (i == 1) {
-			domain->supply = devm_regulator_get(dev, "pu");
-			if (IS_ERR(domain->supply))
-				return PTR_ERR(domain->supply);
-
-			ret = imx_pgc_get_clocks(dev, domain);
-			if (ret)
-				goto clk_err;
-
-			domain->base.power_on(&domain->base);
-		}
-	}
-
-	for (i = 0; i < num_domains; i++)
-		pm_genpd_init(&imx_gpc_domains[i].base, NULL, false);
-
-	if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
-		ret = of_genpd_add_provider_onecell(dev->of_node,
-						    &imx_gpc_onecell_data);
-		if (ret)
-			goto genpd_err;
-	}
-
-	return 0;
-
-genpd_err:
-	for (i = 0; i < num_domains; i++)
-		pm_genpd_remove(&imx_gpc_domains[i].base);
-	imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
-clk_err:
-	return ret;
-}
-
-static int imx_gpc_probe(struct platform_device *pdev)
-{
-	const struct of_device_id *of_id =
-			of_match_device(imx_gpc_dt_ids, &pdev->dev);
-	const struct imx_gpc_dt_data *of_id_data = of_id->data;
-	struct device_node *pgc_node;
-	struct regmap *regmap;
-	void __iomem *base;
-	int ret;
-
-	pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
-
-	/* bail out if DT too old and doesn't provide the necessary info */
-	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
-	    !pgc_node)
-		return 0;
-
-	base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
-
-	regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
-					   &imx_gpc_regmap_config);
-	if (IS_ERR(regmap)) {
-		ret = PTR_ERR(regmap);
-		dev_err(&pdev->dev, "failed to init regmap: %d\n",
-			ret);
-		return ret;
-	}
-
-	/*
-	 * Disable PU power down by runtime PM if ERR009619 is present.
-	 *
-	 * The PRE clock will be paused for several cycles when turning on the
-	 * PU domain LDO from power down state. If PRE is in use at that time,
-	 * the IPU/PRG cannot get the correct display data from the PRE.
-	 *
-	 * This is not a concern when the whole system enters suspend state, so
-	 * it's safe to power down PU in this case.
-	 */
-	if (of_id_data->err009619_present)
-		imx_gpc_domains[GPC_PGC_DOMAIN_PU].base.flags |=
-				GENPD_FLAG_RPM_ALWAYS_ON;
-
-	/* Keep DISP always on if ERR006287 is present */
-	if (of_id_data->err006287_present)
-		imx_gpc_domains[GPC_PGC_DOMAIN_DISPLAY].base.flags |=
-				GENPD_FLAG_ALWAYS_ON;
-
-	if (!pgc_node) {
-		ret = imx_gpc_old_dt_init(&pdev->dev, regmap,
-					  of_id_data->num_domains);
-		if (ret)
-			return ret;
-	} else {
-		struct imx_pm_domain *domain;
-		struct platform_device *pd_pdev;
-		struct device_node *np;
-		struct clk *ipg_clk;
-		unsigned int ipg_rate_mhz;
-		int domain_index;
-
-		ipg_clk = devm_clk_get(&pdev->dev, "ipg");
-		if (IS_ERR(ipg_clk))
-			return PTR_ERR(ipg_clk);
-		ipg_rate_mhz = clk_get_rate(ipg_clk) / 1000000;
-
-		for_each_child_of_node(pgc_node, np) {
-			ret = of_property_read_u32(np, "reg", &domain_index);
-			if (ret) {
-				of_node_put(np);
-				return ret;
-			}
-			if (domain_index >= of_id_data->num_domains)
-				continue;
-
-			pd_pdev = platform_device_alloc("imx-pgc-power-domain",
-							domain_index);
-			if (!pd_pdev) {
-				of_node_put(np);
-				return -ENOMEM;
-			}
-
-			ret = platform_device_add_data(pd_pdev,
-						       &imx_gpc_domains[domain_index],
-						       sizeof(imx_gpc_domains[domain_index]));
-			if (ret) {
-				platform_device_put(pd_pdev);
-				of_node_put(np);
-				return ret;
-			}
-			domain = pd_pdev->dev.platform_data;
-			domain->regmap = regmap;
-			domain->ipg_rate_mhz = ipg_rate_mhz;
-
-			pd_pdev->dev.parent = &pdev->dev;
-			pd_pdev->dev.of_node = np;
-
-			ret = platform_device_add(pd_pdev);
-			if (ret) {
-				platform_device_put(pd_pdev);
-				of_node_put(np);
-				return ret;
-			}
-		}
-	}
-
-	return 0;
-}
-
-static int imx_gpc_remove(struct platform_device *pdev)
-{
-	struct device_node *pgc_node;
-	int ret;
-
-	pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
-
-	/* bail out if DT too old and doesn't provide the necessary info */
-	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
-	    !pgc_node)
-		return 0;
-
-	/*
-	 * If the old DT binding is used the toplevel driver needs to
-	 * de-register the power domains
-	 */
-	if (!pgc_node) {
-		of_genpd_del_provider(pdev->dev.of_node);
-
-		ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
-		if (ret)
-			return ret;
-		imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
-
-		ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static struct platform_driver imx_gpc_driver = {
-	.driver = {
-		.name = "imx-gpc",
-		.of_match_table = imx_gpc_dt_ids,
-	},
-	.probe = imx_gpc_probe,
-	.remove = imx_gpc_remove,
-};
-builtin_platform_driver(imx_gpc_driver)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
deleted file mode 100644
index 4b3300b090a8..000000000000
--- a/drivers/soc/imx/gpcv2.c
+++ /dev/null
@@ -1,1550 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2017 Impinj, Inc
- * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
- *
- * Based on the code of analogus driver:
- *
- * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
- */
-
-#include <linux/clk.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_runtime.h>
-#include <linux/regmap.h>
-#include <linux/regulator/consumer.h>
-#include <linux/reset.h>
-#include <linux/sizes.h>
-#include <dt-bindings/power/imx7-power.h>
-#include <dt-bindings/power/imx8mq-power.h>
-#include <dt-bindings/power/imx8mm-power.h>
-#include <dt-bindings/power/imx8mn-power.h>
-#include <dt-bindings/power/imx8mp-power.h>
-
-#define GPC_LPCR_A_CORE_BSC			0x000
-
-#define GPC_PGC_CPU_MAPPING		0x0ec
-#define IMX8MP_GPC_PGC_CPU_MAPPING	0x1cc
-
-#define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN		BIT(6)
-#define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN		BIT(5)
-#define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN		BIT(4)
-#define IMX7_PCIE_PHY_A_CORE_DOMAIN		BIT(3)
-#define IMX7_MIPI_PHY_A_CORE_DOMAIN		BIT(2)
-
-#define IMX8M_PCIE2_A53_DOMAIN			BIT(15)
-#define IMX8M_MIPI_CSI2_A53_DOMAIN		BIT(14)
-#define IMX8M_MIPI_CSI1_A53_DOMAIN		BIT(13)
-#define IMX8M_DISP_A53_DOMAIN			BIT(12)
-#define IMX8M_HDMI_A53_DOMAIN			BIT(11)
-#define IMX8M_VPU_A53_DOMAIN			BIT(10)
-#define IMX8M_GPU_A53_DOMAIN			BIT(9)
-#define IMX8M_DDR2_A53_DOMAIN			BIT(8)
-#define IMX8M_DDR1_A53_DOMAIN			BIT(7)
-#define IMX8M_OTG2_A53_DOMAIN			BIT(5)
-#define IMX8M_OTG1_A53_DOMAIN			BIT(4)
-#define IMX8M_PCIE1_A53_DOMAIN			BIT(3)
-#define IMX8M_MIPI_A53_DOMAIN			BIT(2)
-
-#define IMX8MM_VPUH1_A53_DOMAIN			BIT(15)
-#define IMX8MM_VPUG2_A53_DOMAIN			BIT(14)
-#define IMX8MM_VPUG1_A53_DOMAIN			BIT(13)
-#define IMX8MM_DISPMIX_A53_DOMAIN		BIT(12)
-#define IMX8MM_VPUMIX_A53_DOMAIN		BIT(10)
-#define IMX8MM_GPUMIX_A53_DOMAIN		BIT(9)
-#define IMX8MM_GPU_A53_DOMAIN			(BIT(8) | BIT(11))
-#define IMX8MM_DDR1_A53_DOMAIN			BIT(7)
-#define IMX8MM_OTG2_A53_DOMAIN			BIT(5)
-#define IMX8MM_OTG1_A53_DOMAIN			BIT(4)
-#define IMX8MM_PCIE_A53_DOMAIN			BIT(3)
-#define IMX8MM_MIPI_A53_DOMAIN			BIT(2)
-
-#define IMX8MN_DISPMIX_A53_DOMAIN		BIT(12)
-#define IMX8MN_GPUMIX_A53_DOMAIN		BIT(9)
-#define IMX8MN_DDR1_A53_DOMAIN		BIT(7)
-#define IMX8MN_OTG1_A53_DOMAIN		BIT(4)
-#define IMX8MN_MIPI_A53_DOMAIN		BIT(2)
-
-#define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN	BIT(20)
-#define IMX8MP_HSIOMIX_A53_DOMAIN		BIT(19)
-#define IMX8MP_MIPI_PHY2_A53_DOMAIN		BIT(18)
-#define IMX8MP_HDMI_PHY_A53_DOMAIN		BIT(17)
-#define IMX8MP_HDMIMIX_A53_DOMAIN		BIT(16)
-#define IMX8MP_VPU_VC8000E_A53_DOMAIN		BIT(15)
-#define IMX8MP_VPU_G2_A53_DOMAIN		BIT(14)
-#define IMX8MP_VPU_G1_A53_DOMAIN		BIT(13)
-#define IMX8MP_MEDIAMIX_A53_DOMAIN		BIT(12)
-#define IMX8MP_GPU3D_A53_DOMAIN			BIT(11)
-#define IMX8MP_VPUMIX_A53_DOMAIN		BIT(10)
-#define IMX8MP_GPUMIX_A53_DOMAIN		BIT(9)
-#define IMX8MP_GPU2D_A53_DOMAIN			BIT(8)
-#define IMX8MP_AUDIOMIX_A53_DOMAIN		BIT(7)
-#define IMX8MP_MLMIX_A53_DOMAIN			BIT(6)
-#define IMX8MP_USB2_PHY_A53_DOMAIN		BIT(5)
-#define IMX8MP_USB1_PHY_A53_DOMAIN		BIT(4)
-#define IMX8MP_PCIE_PHY_A53_DOMAIN		BIT(3)
-#define IMX8MP_MIPI_PHY1_A53_DOMAIN		BIT(2)
-
-#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ	0x0d8
-#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ	0x0e4
-
-#define GPC_PU_PGC_SW_PUP_REQ		0x0f8
-#define GPC_PU_PGC_SW_PDN_REQ		0x104
-
-#define IMX7_USB_HSIC_PHY_SW_Pxx_REQ		BIT(4)
-#define IMX7_USB_OTG2_PHY_SW_Pxx_REQ		BIT(3)
-#define IMX7_USB_OTG1_PHY_SW_Pxx_REQ		BIT(2)
-#define IMX7_PCIE_PHY_SW_Pxx_REQ		BIT(1)
-#define IMX7_MIPI_PHY_SW_Pxx_REQ		BIT(0)
-
-#define IMX8M_PCIE2_SW_Pxx_REQ			BIT(13)
-#define IMX8M_MIPI_CSI2_SW_Pxx_REQ		BIT(12)
-#define IMX8M_MIPI_CSI1_SW_Pxx_REQ		BIT(11)
-#define IMX8M_DISP_SW_Pxx_REQ			BIT(10)
-#define IMX8M_HDMI_SW_Pxx_REQ			BIT(9)
-#define IMX8M_VPU_SW_Pxx_REQ			BIT(8)
-#define IMX8M_GPU_SW_Pxx_REQ			BIT(7)
-#define IMX8M_DDR2_SW_Pxx_REQ			BIT(6)
-#define IMX8M_DDR1_SW_Pxx_REQ			BIT(5)
-#define IMX8M_OTG2_SW_Pxx_REQ			BIT(3)
-#define IMX8M_OTG1_SW_Pxx_REQ			BIT(2)
-#define IMX8M_PCIE1_SW_Pxx_REQ			BIT(1)
-#define IMX8M_MIPI_SW_Pxx_REQ			BIT(0)
-
-#define IMX8MM_VPUH1_SW_Pxx_REQ			BIT(13)
-#define IMX8MM_VPUG2_SW_Pxx_REQ			BIT(12)
-#define IMX8MM_VPUG1_SW_Pxx_REQ			BIT(11)
-#define IMX8MM_DISPMIX_SW_Pxx_REQ		BIT(10)
-#define IMX8MM_VPUMIX_SW_Pxx_REQ		BIT(8)
-#define IMX8MM_GPUMIX_SW_Pxx_REQ		BIT(7)
-#define IMX8MM_GPU_SW_Pxx_REQ			(BIT(6) | BIT(9))
-#define IMX8MM_DDR1_SW_Pxx_REQ			BIT(5)
-#define IMX8MM_OTG2_SW_Pxx_REQ			BIT(3)
-#define IMX8MM_OTG1_SW_Pxx_REQ			BIT(2)
-#define IMX8MM_PCIE_SW_Pxx_REQ			BIT(1)
-#define IMX8MM_MIPI_SW_Pxx_REQ			BIT(0)
-
-#define IMX8MN_DISPMIX_SW_Pxx_REQ		BIT(10)
-#define IMX8MN_GPUMIX_SW_Pxx_REQ		BIT(7)
-#define IMX8MN_DDR1_SW_Pxx_REQ		BIT(5)
-#define IMX8MN_OTG1_SW_Pxx_REQ		BIT(2)
-#define IMX8MN_MIPI_SW_Pxx_REQ		BIT(0)
-
-#define IMX8MP_DDRMIX_Pxx_REQ			BIT(19)
-#define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ		BIT(18)
-#define IMX8MP_HSIOMIX_Pxx_REQ			BIT(17)
-#define IMX8MP_MIPI_PHY2_Pxx_REQ		BIT(16)
-#define IMX8MP_HDMI_PHY_Pxx_REQ			BIT(15)
-#define IMX8MP_HDMIMIX_Pxx_REQ			BIT(14)
-#define IMX8MP_VPU_VC8K_Pxx_REQ			BIT(13)
-#define IMX8MP_VPU_G2_Pxx_REQ			BIT(12)
-#define IMX8MP_VPU_G1_Pxx_REQ			BIT(11)
-#define IMX8MP_MEDIMIX_Pxx_REQ			BIT(10)
-#define IMX8MP_GPU_3D_Pxx_REQ			BIT(9)
-#define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ	BIT(8)
-#define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ		BIT(7)
-#define IMX8MP_GPU_2D_Pxx_REQ			BIT(6)
-#define IMX8MP_AUDIOMIX_Pxx_REQ			BIT(5)
-#define IMX8MP_MLMIX_Pxx_REQ			BIT(4)
-#define IMX8MP_USB2_PHY_Pxx_REQ			BIT(3)
-#define IMX8MP_USB1_PHY_Pxx_REQ			BIT(2)
-#define IMX8MP_PCIE_PHY_SW_Pxx_REQ		BIT(1)
-#define IMX8MP_MIPI_PHY1_SW_Pxx_REQ		BIT(0)
-
-#define GPC_M4_PU_PDN_FLG		0x1bc
-
-#define IMX8MP_GPC_PU_PWRHSK		0x190
-#define GPC_PU_PWRHSK			0x1fc
-
-#define IMX8M_GPU_HSK_PWRDNACKN			BIT(26)
-#define IMX8M_VPU_HSK_PWRDNACKN			BIT(25)
-#define IMX8M_DISP_HSK_PWRDNACKN		BIT(24)
-#define IMX8M_GPU_HSK_PWRDNREQN			BIT(6)
-#define IMX8M_VPU_HSK_PWRDNREQN			BIT(5)
-#define IMX8M_DISP_HSK_PWRDNREQN		BIT(4)
-
-#define IMX8MM_GPUMIX_HSK_PWRDNACKN		BIT(29)
-#define IMX8MM_GPU_HSK_PWRDNACKN		(BIT(27) | BIT(28))
-#define IMX8MM_VPUMIX_HSK_PWRDNACKN		BIT(26)
-#define IMX8MM_DISPMIX_HSK_PWRDNACKN		BIT(25)
-#define IMX8MM_HSIO_HSK_PWRDNACKN		(BIT(23) | BIT(24))
-#define IMX8MM_GPUMIX_HSK_PWRDNREQN		BIT(11)
-#define IMX8MM_GPU_HSK_PWRDNREQN		(BIT(9) | BIT(10))
-#define IMX8MM_VPUMIX_HSK_PWRDNREQN		BIT(8)
-#define IMX8MM_DISPMIX_HSK_PWRDNREQN		BIT(7)
-#define IMX8MM_HSIO_HSK_PWRDNREQN		(BIT(5) | BIT(6))
-
-#define IMX8MN_GPUMIX_HSK_PWRDNACKN		(BIT(29) | BIT(27))
-#define IMX8MN_DISPMIX_HSK_PWRDNACKN		BIT(25)
-#define IMX8MN_HSIO_HSK_PWRDNACKN		BIT(23)
-#define IMX8MN_GPUMIX_HSK_PWRDNREQN		(BIT(11) | BIT(9))
-#define IMX8MN_DISPMIX_HSK_PWRDNREQN		BIT(7)
-#define IMX8MN_HSIO_HSK_PWRDNREQN		BIT(5)
-
-#define IMX8MP_MEDIAMIX_PWRDNACKN		BIT(30)
-#define IMX8MP_HDMIMIX_PWRDNACKN		BIT(29)
-#define IMX8MP_HSIOMIX_PWRDNACKN		BIT(28)
-#define IMX8MP_VPUMIX_PWRDNACKN			BIT(26)
-#define IMX8MP_GPUMIX_PWRDNACKN			BIT(25)
-#define IMX8MP_MLMIX_PWRDNACKN			(BIT(23) | BIT(24))
-#define IMX8MP_AUDIOMIX_PWRDNACKN		(BIT(20) | BIT(31))
-#define IMX8MP_MEDIAMIX_PWRDNREQN		BIT(14)
-#define IMX8MP_HDMIMIX_PWRDNREQN		BIT(13)
-#define IMX8MP_HSIOMIX_PWRDNREQN		BIT(12)
-#define IMX8MP_VPUMIX_PWRDNREQN			BIT(10)
-#define IMX8MP_GPUMIX_PWRDNREQN			BIT(9)
-#define IMX8MP_MLMIX_PWRDNREQN			(BIT(7) | BIT(8))
-#define IMX8MP_AUDIOMIX_PWRDNREQN		(BIT(4) | BIT(15))
-
-/*
- * The PGC offset values in Reference Manual
- * (Rev. 1, 01/2018 and the older ones) GPC chapter's
- * GPC_PGC memory map are incorrect, below offset
- * values are from design RTL.
- */
-#define IMX7_PGC_MIPI			16
-#define IMX7_PGC_PCIE			17
-#define IMX7_PGC_USB_HSIC		20
-
-#define IMX8M_PGC_MIPI			16
-#define IMX8M_PGC_PCIE1			17
-#define IMX8M_PGC_OTG1			18
-#define IMX8M_PGC_OTG2			19
-#define IMX8M_PGC_DDR1			21
-#define IMX8M_PGC_GPU			23
-#define IMX8M_PGC_VPU			24
-#define IMX8M_PGC_DISP			26
-#define IMX8M_PGC_MIPI_CSI1		27
-#define IMX8M_PGC_MIPI_CSI2		28
-#define IMX8M_PGC_PCIE2			29
-
-#define IMX8MM_PGC_MIPI			16
-#define IMX8MM_PGC_PCIE			17
-#define IMX8MM_PGC_OTG1			18
-#define IMX8MM_PGC_OTG2			19
-#define IMX8MM_PGC_DDR1			21
-#define IMX8MM_PGC_GPU2D		22
-#define IMX8MM_PGC_GPUMIX		23
-#define IMX8MM_PGC_VPUMIX		24
-#define IMX8MM_PGC_GPU3D		25
-#define IMX8MM_PGC_DISPMIX		26
-#define IMX8MM_PGC_VPUG1		27
-#define IMX8MM_PGC_VPUG2		28
-#define IMX8MM_PGC_VPUH1		29
-
-#define IMX8MN_PGC_MIPI		16
-#define IMX8MN_PGC_OTG1		18
-#define IMX8MN_PGC_DDR1		21
-#define IMX8MN_PGC_GPUMIX		23
-#define IMX8MN_PGC_DISPMIX		26
-
-#define IMX8MP_PGC_NOC			9
-#define IMX8MP_PGC_MIPI1		12
-#define IMX8MP_PGC_PCIE			13
-#define IMX8MP_PGC_USB1			14
-#define IMX8MP_PGC_USB2			15
-#define IMX8MP_PGC_MLMIX		16
-#define IMX8MP_PGC_AUDIOMIX		17
-#define IMX8MP_PGC_GPU2D		18
-#define IMX8MP_PGC_GPUMIX		19
-#define IMX8MP_PGC_VPUMIX		20
-#define IMX8MP_PGC_GPU3D		21
-#define IMX8MP_PGC_MEDIAMIX		22
-#define IMX8MP_PGC_VPU_G1		23
-#define IMX8MP_PGC_VPU_G2		24
-#define IMX8MP_PGC_VPU_VC8000E		25
-#define IMX8MP_PGC_HDMIMIX		26
-#define IMX8MP_PGC_HDMI			27
-#define IMX8MP_PGC_MIPI2		28
-#define IMX8MP_PGC_HSIOMIX		29
-#define IMX8MP_PGC_MEDIA_ISP_DWP	30
-#define IMX8MP_PGC_DDRMIX		31
-
-#define GPC_PGC_CTRL(n)			(0x800 + (n) * 0x40)
-#define GPC_PGC_SR(n)			(GPC_PGC_CTRL(n) + 0xc)
-
-#define GPC_PGC_CTRL_PCR		BIT(0)
-
-struct imx_pgc_regs {
-	u16 map;
-	u16 pup;
-	u16 pdn;
-	u16 hsk;
-};
-
-struct imx_pgc_domain {
-	struct generic_pm_domain genpd;
-	struct regmap *regmap;
-	const struct imx_pgc_regs *regs;
-	struct regulator *regulator;
-	struct reset_control *reset;
-	struct clk_bulk_data *clks;
-	int num_clks;
-
-	unsigned long pgc;
-
-	const struct {
-		u32 pxx;
-		u32 map;
-		u32 hskreq;
-		u32 hskack;
-	} bits;
-
-	const int voltage;
-	const bool keep_clocks;
-	struct device *dev;
-
-	unsigned int pgc_sw_pup_reg;
-	unsigned int pgc_sw_pdn_reg;
-};
-
-struct imx_pgc_domain_data {
-	const struct imx_pgc_domain *domains;
-	size_t domains_num;
-	const struct regmap_access_table *reg_access_table;
-	const struct imx_pgc_regs *pgc_regs;
-};
-
-static inline struct imx_pgc_domain *
-to_imx_pgc_domain(struct generic_pm_domain *genpd)
-{
-	return container_of(genpd, struct imx_pgc_domain, genpd);
-}
-
-static int imx_pgc_power_up(struct generic_pm_domain *genpd)
-{
-	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
-	u32 reg_val, pgc;
-	int ret;
-
-	ret = pm_runtime_get_sync(domain->dev);
-	if (ret < 0) {
-		pm_runtime_put_noidle(domain->dev);
-		return ret;
-	}
-
-	if (!IS_ERR(domain->regulator)) {
-		ret = regulator_enable(domain->regulator);
-		if (ret) {
-			dev_err(domain->dev,
-				"failed to enable regulator: %pe\n",
-				ERR_PTR(ret));
-			goto out_put_pm;
-		}
-	}
-
-	reset_control_assert(domain->reset);
-
-	/* Enable reset clocks for all devices in the domain */
-	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
-	if (ret) {
-		dev_err(domain->dev, "failed to enable reset clocks\n");
-		goto out_regulator_disable;
-	}
-
-	/* delays for reset to propagate */
-	udelay(5);
-
-	if (domain->bits.pxx) {
-		/* request the domain to power up */
-		regmap_update_bits(domain->regmap, domain->regs->pup,
-				   domain->bits.pxx, domain->bits.pxx);
-		/*
-		 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
-		 * for PUP_REQ/PDN_REQ bit to be cleared
-		 */
-		ret = regmap_read_poll_timeout(domain->regmap,
-					       domain->regs->pup, reg_val,
-					       !(reg_val & domain->bits.pxx),
-					       0, USEC_PER_MSEC);
-		if (ret) {
-			dev_err(domain->dev, "failed to command PGC\n");
-			goto out_clk_disable;
-		}
-
-		/* disable power control */
-		for_each_set_bit(pgc, &domain->pgc, 32) {
-			regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
-					  GPC_PGC_CTRL_PCR);
-		}
-	}
-
-	/* delay for reset to propagate */
-	udelay(5);
-
-	reset_control_deassert(domain->reset);
-
-	/* request the ADB400 to power up */
-	if (domain->bits.hskreq) {
-		regmap_update_bits(domain->regmap, domain->regs->hsk,
-				   domain->bits.hskreq, domain->bits.hskreq);
-
-		/*
-		 * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
-		 *				  (reg_val & domain->bits.hskack), 0,
-		 *				  USEC_PER_MSEC);
-		 * Technically we need the commented code to wait handshake. But that needs
-		 * the BLK-CTL module BUS clk-en bit being set.
-		 *
-		 * There is a separate BLK-CTL module and we will have such a driver for it,
-		 * that driver will set the BUS clk-en bit and handshake will be triggered
-		 * automatically there. Just add a delay and suppose the handshake finish
-		 * after that.
-		 */
-	}
-
-	/* Disable reset clocks for all devices in the domain */
-	if (!domain->keep_clocks)
-		clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
-
-	return 0;
-
-out_clk_disable:
-	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
-out_regulator_disable:
-	if (!IS_ERR(domain->regulator))
-		regulator_disable(domain->regulator);
-out_put_pm:
-	pm_runtime_put(domain->dev);
-
-	return ret;
-}
-
-static int imx_pgc_power_down(struct generic_pm_domain *genpd)
-{
-	struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
-	u32 reg_val, pgc;
-	int ret;
-
-	/* Enable reset clocks for all devices in the domain */
-	if (!domain->keep_clocks) {
-		ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
-		if (ret) {
-			dev_err(domain->dev, "failed to enable reset clocks\n");
-			return ret;
-		}
-	}
-
-	/* request the ADB400 to power down */
-	if (domain->bits.hskreq) {
-		regmap_clear_bits(domain->regmap, domain->regs->hsk,
-				  domain->bits.hskreq);
-
-		ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk,
-					       reg_val,
-					       !(reg_val & domain->bits.hskack),
-					       0, USEC_PER_MSEC);
-		if (ret) {
-			dev_err(domain->dev, "failed to power down ADB400\n");
-			goto out_clk_disable;
-		}
-	}
-
-	if (domain->bits.pxx) {
-		/* enable power control */
-		for_each_set_bit(pgc, &domain->pgc, 32) {
-			regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
-					   GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
-		}
-
-		/* request the domain to power down */
-		regmap_update_bits(domain->regmap, domain->regs->pdn,
-				   domain->bits.pxx, domain->bits.pxx);
-		/*
-		 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
-		 * for PUP_REQ/PDN_REQ bit to be cleared
-		 */
-		ret = regmap_read_poll_timeout(domain->regmap,
-					       domain->regs->pdn, reg_val,
-					       !(reg_val & domain->bits.pxx),
-					       0, USEC_PER_MSEC);
-		if (ret) {
-			dev_err(domain->dev, "failed to command PGC\n");
-			goto out_clk_disable;
-		}
-	}
-
-	/* Disable reset clocks for all devices in the domain */
-	clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
-
-	if (!IS_ERR(domain->regulator)) {
-		ret = regulator_disable(domain->regulator);
-		if (ret) {
-			dev_err(domain->dev,
-				"failed to disable regulator: %pe\n",
-				ERR_PTR(ret));