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| author | Laura Garcia Liebana <nevola@gmail.com> | 2016-02-17 09:51:32 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-02-20 14:59:37 -0800 |
| commit | a5cecac645c7eb18e0c23d6c52662cbe07b6d232 (patch) | |
| tree | de3e93a313815fc904f26345c76f36aafbabe222 /drivers/staging/netlogic | |
| parent | 06409808e3da79c42320e2dfb17a7a424c2fdfcb (diff) | |
| download | linux-a5cecac645c7eb18e0c23d6c52662cbe07b6d232.tar.gz linux-a5cecac645c7eb18e0c23d6c52662cbe07b6d232.tar.bz2 linux-a5cecac645c7eb18e0c23d6c52662cbe07b6d232.zip | |
staging: netlogic: Fix CamelCase for constants
Avoid the use of CamelCase for constants. Checkpatch detected these
issues.
Signed-off-by: Laura Garcia Liebana <nevola@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/netlogic')
| -rw-r--r-- | drivers/staging/netlogic/xlr_net.c | 30 | ||||
| -rw-r--r-- | drivers/staging/netlogic/xlr_net.h | 978 |
2 files changed, 504 insertions, 504 deletions
diff --git a/drivers/staging/netlogic/xlr_net.c b/drivers/staging/netlogic/xlr_net.c index 425ac539507c..cd66dd1cb39c 100644 --- a/drivers/staging/netlogic/xlr_net.c +++ b/drivers/staging/netlogic/xlr_net.c @@ -932,13 +932,13 @@ static void xlr_port_enable(struct xlr_net_priv *priv) /* Setup tx control reg */ xlr_reg_update(priv->base_addr, R_TX_CONTROL, - ((1 << O_TX_CONTROL__TxEnable) | - (512 << O_TX_CONTROL__TxThreshold)), 0x3fff); + ((1 << O_TX_CONTROL__TXENABLE) | + (512 << O_TX_CONTROL__TXTHRESHOLD)), 0x3fff); /* Setup rx control reg */ xlr_reg_update(priv->base_addr, R_RX_CONTROL, - 1 << O_RX_CONTROL__RxEnable, - 1 << O_RX_CONTROL__RxEnable); + 1 << O_RX_CONTROL__RXENABLE, + 1 << O_RX_CONTROL__RXENABLE); } static void xlr_port_disable(struct xlr_net_priv *priv) @@ -953,12 +953,12 @@ static void xlr_port_disable(struct xlr_net_priv *priv) /* Setup tx control reg */ xlr_reg_update(priv->base_addr, R_TX_CONTROL, - ((1 << O_TX_CONTROL__TxEnable) | - (512 << O_TX_CONTROL__TxThreshold)), 0); + ((1 << O_TX_CONTROL__TXENABLE) | + (512 << O_TX_CONTROL__TXTHRESHOLD)), 0); /* Setup rx control reg */ xlr_reg_update(priv->base_addr, R_RX_CONTROL, - 1 << O_RX_CONTROL__RxEnable, 0); + 1 << O_RX_CONTROL__RXENABLE, 0); } /* @@ -974,9 +974,9 @@ static int xlr_gmac_init(struct xlr_net_priv *priv, xlr_port_disable(priv); xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL, - (1 << O_DESC_PACK_CTRL__MaxEntry) | - (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset) | - (1600 << O_DESC_PACK_CTRL__RegularSize)); + (1 << O_DESC_PACK_CTRL__MAXENTRY) | + (BYTE_OFFSET << O_DESC_PACK_CTRL__BYTEOFFSET) | + (1600 << O_DESC_PACK_CTRL__REGULARSIZE)); ret = xlr_setup_mdio(priv, pdev); if (ret) @@ -988,13 +988,13 @@ static int xlr_gmac_init(struct xlr_net_priv *priv, /* speed 2.5Mhz */ xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02); /* Setup Interrupt mask reg */ - xlr_nae_wreg(priv->base_addr, R_INTMASK, (1 << O_INTMASK__TxIllegal) | - (1 << O_INTMASK__MDInt) | (1 << O_INTMASK__TxFetchError) | - (1 << O_INTMASK__P2PSpillEcc) | (1 << O_INTMASK__TagFull) | - (1 << O_INTMASK__Underrun) | (1 << O_INTMASK__Abort)); + xlr_nae_wreg(priv->base_addr, R_INTMASK, (1 << O_INTMASK__TXILLEGAL) | + (1 << O_INTMASK__MDINT) | (1 << O_INTMASK__TXFETCHERROR) | + (1 << O_INTMASK__P2PSPILLECC) | (1 << O_INTMASK__TAGFULL) | + (1 << O_INTMASK__UNDERRUN) | (1 << O_INTMASK__ABORT)); /* Clear all stats */ - xlr_reg_update(priv->base_addr, R_STATCTRL, 0, 1 << O_STATCTRL__ClrCnt); + xlr_reg_update(priv->base_addr, R_STATCTRL, 0, 1 << O_STATCTRL__CLRCNT); xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, 1 << 2); return 0; } diff --git a/drivers/staging/netlogic/xlr_net.h b/drivers/staging/netlogic/xlr_net.h index 7ae8874daee8..f76e16cfd15d 100644 --- a/drivers/staging/netlogic/xlr_net.h +++ b/drivers/staging/netlogic/xlr_net.h @@ -277,332 +277,332 @@ #define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0 #define R_HASH_TABLE_VECTOR 0x30 #define R_TX_CONTROL 0x0A0 -#define O_TX_CONTROL__Tx15Halt 31 -#define O_TX_CONTROL__Tx14Halt 30 -#define O_TX_CONTROL__Tx13Halt 29 -#define O_TX_CONTROL__Tx12Halt 28 -#define O_TX_CONTROL__Tx11Halt 27 -#define O_TX_CONTROL__Tx10Halt 26 -#define O_TX_CONTROL__Tx9Halt 25 -#define O_TX_CONTROL__Tx8Halt 24 -#define O_TX_CONTROL__Tx7Halt 23 -#define O_TX_CONTROL__Tx6Halt 22 -#define O_TX_CONTROL__Tx5Halt 21 -#define O_TX_CONTROL__Tx4Halt 20 -#define O_TX_CONTROL__Tx3Halt 19 -#define O_TX_CONTROL__Tx2Halt 18 -#define O_TX_CONTROL__Tx1Halt 17 -#define O_TX_CONTROL__Tx0Halt 16 -#define O_TX_CONTROL__TxIdle 15 -#define O_TX_CONTROL__TxEnable 14 -#define O_TX_CONTROL__TxThreshold 0 -#define W_TX_CONTROL__TxThreshold 14 +#define O_TX_CONTROL__TX15HALT 31 +#define O_TX_CONTROL__TX14HALT 30 +#define O_TX_CONTROL__TX13HALT 29 +#define O_TX_CONTROL__TX12HALT 28 +#define O_TX_CONTROL__TX11HALT 27 +#define O_TX_CONTROL__TX10HALT 26 +#define O_TX_CONTROL__TX9HALT 25 +#define O_TX_CONTROL__TX8HALT 24 +#define O_TX_CONTROL__TX7HALT 23 +#define O_TX_CONTROL__TX6HALT 22 +#define O_TX_CONTROL__TX5HALT 21 +#define O_TX_CONTROL__TX4HALT 20 +#define O_TX_CONTROL__TX3HALT 19 +#define O_TX_CONTROL__TX2HALT 18 +#define O_TX_CONTROL__TX1HALT 17 +#define O_TX_CONTROL__TX0HALT 16 +#define O_TX_CONTROL__TXIDLE 15 +#define O_TX_CONTROL__TXENABLE 14 +#define O_TX_CONTROL__TXTHRESHOLD 0 +#define W_TX_CONTROL__TXTHRESHOLD 14 #define R_RX_CONTROL 0x0A1 #define O_RX_CONTROL__RGMII 10 -#define O_RX_CONTROL__SoftReset 2 -#define O_RX_CONTROL__RxHalt 1 -#define O_RX_CONTROL__RxEnable 0 +#define O_RX_CONTROL__SOFTRESET 2 +#define O_RX_CONTROL__RXHALT 1 +#define O_RX_CONTROL__RXENABLE 0 #define R_DESC_PACK_CTRL 0x0A2 -#define O_DESC_PACK_CTRL__ByteOffset 17 -#define W_DESC_PACK_CTRL__ByteOffset 3 -#define O_DESC_PACK_CTRL__PrePadEnable 16 -#define O_DESC_PACK_CTRL__MaxEntry 14 -#define W_DESC_PACK_CTRL__MaxEntry 2 -#define O_DESC_PACK_CTRL__RegularSize 0 -#define W_DESC_PACK_CTRL__RegularSize 14 +#define O_DESC_PACK_CTRL__BYTEOFFSET 17 +#define W_DESC_PACK_CTRL__BYTEOFFSET 3 +#define O_DESC_PACK_CTRL__PREPADENABLE 16 +#define O_DESC_PACK_CTRL__MAXENTRY 14 +#define W_DESC_PACK_CTRL__MAXENTRY 2 +#define O_DESC_PACK_CTRL__REGULARSIZE 0 +#define W_DESC_PACK_CTRL__REGULARSIZE 14 #define R_STATCTRL 0x0A3 -#define O_STATCTRL__OverFlowEn 4 +#define O_STATCTRL__OVERFLOWEN 4 #define O_STATCTRL__GIG 3 -#define O_STATCTRL__Sten 2 -#define O_STATCTRL__ClrCnt 1 -#define O_STATCTRL__AutoZ 0 +#define O_STATCTRL__STEN 2 +#define O_STATCTRL__CLRCNT 1 +#define O_STATCTRL__AUTOZ 0 #define R_L2ALLOCCTRL 0x0A4 -#define O_L2ALLOCCTRL__TxL2Allocate 9 -#define W_L2ALLOCCTRL__TxL2Allocate 9 -#define O_L2ALLOCCTRL__RxL2Allocate 0 -#define W_L2ALLOCCTRL__RxL2Allocate 9 +#define O_L2ALLOCCTRL__TXL2ALLOCATE 9 +#define W_L2ALLOCCTRL__TXL2ALLOCATE 9 +#define O_L2ALLOCCTRL__RXL2ALLOCATE 0 +#define W_L2ALLOCCTRL__RXL2ALLOCATE 9 #define R_INTMASK 0x0A5 -#define O_INTMASK__Spi4TxError 28 -#define O_INTMASK__Spi4RxError 27 -#define O_INTMASK__RGMIIHalfDupCollision 27 -#define O_INTMASK__Abort 26 -#define O_INTMASK__Underrun 25 -#define O_INTMASK__DiscardPacket 24 -#define O_INTMASK__AsyncFifoFull 23 -#define O_INTMASK__TagFull 22 -#define O_INTMASK__Class3Full 21 -#define O_INTMASK__C3EarlyFull 20 -#define O_INTMASK__Class2Full 19 -#define O_INTMASK__C2EarlyFull 18 -#define O_INTMASK__Class1Full 17 -#define O_INTMASK__C1EarlyFull 16 -#define O_INTMASK__Class0Full 15 -#define O_INTMASK__C0EarlyFull 14 -#define O_INTMASK__RxDataFull 13 -#define O_INTMASK__RxEarlyFull 12 -#define O_INTMASK__RFreeEmpty 9 -#define O_INTMASK__RFEarlyEmpty 8 -#define O_INTMASK__P2PSpillEcc 7 -#define O_INTMASK__FreeDescFull 5 -#define O_INTMASK__FreeEarlyFull 4 -#define O_INTMASK__TxFetchError 3 -#define O_INTMASK__StatCarry 2 -#define O_INTMASK__MDInt 1 -#define O_INTMASK__TxIllegal 0 +#define O_INTMASK__SPI4TXERROR 28 +#define O_INTMASK__SPI4RXERROR 27 +#define O_INTMASK__RGMIIHALFDUPCOLLISION 27 +#define O_INTMASK__ABORT 26 +#define O_INTMASK__UNDERRUN 25 +#define O_INTMASK__DISCARDPACKET 24 +#define O_INTMASK__ASYNCFIFOFULL 23 +#define O_INTMASK__TAGFULL 22 +#define O_INTMASK__CLASS3FULL 21 +#define O_INTMASK__C3EARLYFULL 20 +#define O_INTMASK__CLASS2FULL 19 +#define O_INTMASK__C2EARLYFULL 18 +#define O_INTMASK__CLASS1FULL 17 +#define O_INTMASK__C1EARLYFULL 16 +#define O_INTMASK__CLASS0FULL 15 +#define O_INTMASK__C0EARLYFULL 14 +#define O_INTMASK__RXDATAFULL 13 +#define O_INTMASK__RXEARLYFULL 12 +#define O_INTMASK__RFREEEMPTY 9 +#define O_INTMASK__RFEARLYEMPTY 8 +#define O_INTMASK__P2PSPILLECC 7 +#define O_INTMASK__FREEDESCFULL 5 +#define O_INTMASK__FREEEARLYFULL 4 +#define O_INTMASK__TXFETCHERROR 3 +#define O_INTMASK__STATCARRY 2 +#define O_INTMASK__MDINT 1 +#define O_INTMASK__TXILLEGAL 0 #define R_INTREG 0x0A6 -#define O_INTREG__Spi4TxError 28 -#define O_INTREG__Spi4RxError 27 -#define O_INTREG__RGMIIHalfDupCollision 27 -#define O_INTREG__Abort 26 -#define O_INTREG__Underrun 25 -#define O_INTREG__DiscardPacket 24 -#define O_INTREG__AsyncFifoFull 23 -#define O_INTREG__TagFull 22 -#define O_INTREG__Class3Full 21 -#define O_INTREG__C3EarlyFull 20 -#define O_INTREG__Class2Full 19 -#define O_INTREG__C2EarlyFull 18 -#define O_INTREG__Class1Full 17 -#define O_INTREG__C1EarlyFull 16 -#define O_INTREG__Class0Full 15 -#define O_INTREG__C0EarlyFull 14 -#define O_INTREG__RxDataFull 13 -#define O_INTREG__RxEarlyFull 12 -#define O_INTREG__RFreeEmpty 9 -#define O_INTREG__RFEarlyEmpty 8 -#define O_INTREG__P2PSpillEcc 7 -#define O_INTREG__FreeDescFull 5 -#define O_INTREG__FreeEarlyFull 4 -#define O_INTREG__TxFetchError 3 -#define O_INTREG__StatCarry 2 -#define O_INTREG__MDInt 1 -#define O_INTREG__TxIllegal 0 +#define O_INTREG__SPI4TXERROR 28 +#define O_INTREG__SPI4RXERROR 27 +#define O_INTREG__RGMIIHALFDUPCOLLISION 27 +#define O_INTREG__ABORT 26 +#define O_INTREG__UNDERRUN 25 +#define O_INTREG__DISCARDPACKET 24 +#define O_INTREG__ASYNCFIFOFULL 23 +#define O_INTREG__TAGFULL 22 +#define O_INTREG__CLASS3FULL 21 +#define O_INTREG__C3EARLYFULL 20 +#define O_INTREG__CLASS2FULL 19 +#define O_INTREG__C2EARLYFULL 18 +#define O_INTREG__CLASS1FULL 17 +#define O_INTREG__C1EARLYFULL 16 +#define O_INTREG__CLASS0FULL 15 +#define O_INTREG__C0EARLYFULL 14 +#define O_INTREG__RXDATAFULL 13 +#define O_INTREG__RXEARLYFULL 12 +#define O_INTREG__RFREEEMPTY 9 +#define O_INTREG__RFEARLYEMPTY 8 +#define O_INTREG__P2PSPILLECC 7 +#define O_INTREG__FREEDESCFULL 5 +#define O_INTREG__FREEEARLYFULL 4 +#define O_INTREG__TXFETCHERROR 3 +#define O_INTREG__STATCARRY 2 +#define O_INTREG__MDINT 1 +#define O_INTREG__TXILLEGAL 0 #define R_TXRETRY 0x0A7 -#define O_TXRETRY__CollisionRetry 6 -#define O_TXRETRY__BusErrorRetry 5 -#define O_TXRETRY__UnderRunRetry 4 -#define O_TXRETRY__Retries 0 -#define W_TXRETRY__Retries 4 +#define O_TXRETRY__COLLISIONRETRY 6 +#define O_TXRETRY__BUSERRORRETRY 5 +#define O_TXRETRY__UNDERRUNRETRY 4 +#define O_TXRETRY__RETRIES 0 +#define W_TXRETRY__RETRIES 4 #define R_CORECONTROL 0x0A8 -#define O_CORECONTROL__ErrorThread 4 -#define W_CORECONTROL__ErrorThread 7 -#define O_CORECONTROL__Shutdown 2 -#define O_CORECONTROL__Speed 0 -#define W_CORECONTROL__Speed 2 +#define O_CORECONTROL__ERRORTHREAD 4 +#define W_CORECONTROL__ERRORTHREAD 7 +#define O_CORECONTROL__SHUTDOWN 2 +#define O_CORECONTROL__SPEED 0 +#define W_CORECONTROL__SPEED 2 #define R_BYTEOFFSET0 0x0A9 #define R_BYTEOFFSET1 0x0AA #define R_L2TYPE_0 0x0F0 -#define O_L2TYPE__ExtraHdrProtoSize 26 -#define W_L2TYPE__ExtraHdrProtoSize 5 -#define O_L2TYPE__ExtraHdrProtoOffset 20 -#define W_L2TYPE__ExtraHdrProtoOffset 6 -#define O_L2TYPE__ExtraHeaderSize 14 -#define W_L2TYPE__ExtraHeaderSize 6 -#define O_L2TYPE__ProtoOffset 8 -#define W_L2TYPE__ProtoOffset 6 -#define O_L2TYPE__L2HdrOffset 2 -#define W_L2TYPE__L2HdrOffset 6 -#define O_L2TYPE__L2Proto 0 -#define W_L2TYPE__L2Proto 2 +#define O_L2TYPE__EXTRAHDRPROTOSIZE 26 +#define W_L2TYPE__EXTRAHDRPROTOSIZE 5 +#define O_L2TYPE__EXTRAHDRPROTOOFFSET 20 +#define W_L2TYPE__EXTRAHDRPROTOOFFSET 6 +#define O_L2TYPE__EXTRAHEADERSIZE 14 +#define W_L2TYPE__EXTRAHEADERSIZE 6 +#define O_L2TYPE__PROTOOFFSET 8 +#define W_L2TYPE__PROTOOFFSET 6 +#define O_L2TYPE__L2HDROFFSET 2 +#define W_L2TYPE__L2HDROFFSET 6 +#define O_L2TYPE__L2PROTO 0 +#define W_L2TYPE__L2PROTO 2 #define R_L2TYPE_1 0xF0 #define R_L2TYPE_2 0xF0 #define R_L2TYPE_3 0xF0 #define R_PARSERCONFIGREG 0x100 -#define O_PARSERCONFIGREG__CRCHashPoly 8 -#define W_PARSERCONFIGREG__CRCHashPoly 7 -#define O_PARSERCONFIGREG__PrePadOffset 4 -#define W_PARSERCONFIGREG__PrePadOffset 4 -#define O_PARSERCONFIGREG__UseCAM 2 -#define O_PARSERCONFIGREG__UseHASH 1 -#define O_PARSERCONFIGREG__UseProto 0 +#define O_PARSERCONFIGREG__CRCHASHPOLY 8 +#define W_PARSERCONFIGREG__CRCHASHPOLY 7 +#define O_PARSERCONFIGREG__PREPADOFFSET 4 +#define W_PARSERCONFIGREG__PREPADOFFSET 4 +#define O_PARSERCONFIGREG__USECAM 2 +#define O_PARSERCONFIGREG__USEHASH 1 +#define O_PARSERCONFIGREG__USEPROTO 0 #define R_L3CTABLE 0x140 -#define O_L3CTABLE__Offset0 25 -#define W_L3CTABLE__Offset0 7 -#define O_L3CTABLE__Len0 21 -#define W_L3CTABLE__Len0 4 -#define O_L3CTABLE__Offset1 14 -#define W_L3CTABLE__Offset1 7 -#define O_L3CTABLE__Len1 10 -#define W_L3CTABLE__Len1 4 -#define O_L3CTABLE__Offset2 4 -#define W_L3CTABLE__Offset2 6 -#define O_L3CTABLE__Len2 0 -#define W_L3CTABLE__Len2 4 -#define O_L3CTABLE__L3HdrOffset 26 -#define W_L3CTABLE__L3HdrOffset 6 -#define O_L3CTABLE__L4ProtoOffset 20 -#define W_L3CTABLE__L4ProtoOffset 6 -#define O_L3CTABLE__IPChksumCompute 19 -#define O_L3CTABLE__L4Classify 18 -#define O_L3CTABLE__L2Proto 16 -#define W_L3CTABLE__L2Proto 2 -#define O_L3CTABLE__L3ProtoKey 0 -#define W_L3CTABLE__L3ProtoKey 16 +#define O_L3CTABLE__OFFSET0 25 +#define W_L3CTABLE__OFFSET0 7 +#define O_L3CTABLE__LEN0 21 +#define W_L3CTABLE__LEN0 4 +#define O_L3CTABLE__OFFSET1 14 +#define W_L3CTABLE__OFFSET1 7 +#define O_L3CTABLE__LEN1 10 +#define W_L3CTABLE__LEN1 4 +#define O_L3CTABLE__OFFSET2 4 +#define W_L3CTABLE__OFFSET2 6 +#define O_L3CTABLE__LEN2 0 +#define W_L3CTABLE__LEN2 4 +#define O_L3CTABLE__L3HDROFFSET 26 +#define W_L3CTABLE__L3HDROFFSET 6 +#define O_L3CTABLE__L4PROTOOFFSET 20 +#define W_L3CTABLE__L4PROTOOFFSET 6 +#define O_L3CTABLE__IPCHKSUMCOMPUTE 19 +#define O_L3CTABLE__L4CLASSIFY 18 +#define O_L3CTABLE__L2PROTO 16 +#define W_L3CTABLE__L2PROTO 2 +#define O_L3CTABLE__L3PROTOKEY 0 +#define W_L3CTABLE__L3PROTOKEY 16 #define R_L4CTABLE 0x160 -#define O_L4CTABLE__Offset0 21 -#define W_L4CTABLE__Offset0 6 -#define O_L4CTABLE__Len0 17 -#define W_L4CTABLE__Len0 4 -#define O_L4CTABLE__Offset1 11 -#define W_L4CTABLE__Offset1 6 -#define O_L4CTABLE__Len1 7 -#define W_L4CTABLE__Len1 4 -#define O_L4CTABLE__TCPChksumEnable 0 +#define O_L4CTABLE__OFFSET0 21 +#define W_L4CTABLE__OFFSET0 6 +#define O_L4CTABLE__LEN0 17 +#define W_L4CTABLE__LEN0 4 +#define O_L4CTABLE__OFFSET1 11 +#define W_L4CTABLE__OFFSET1 6 +#define O_L4CTABLE__LEN1 7 +#define W_L4CTABLE__LEN1 4 +#define O_L4CTABLE__TCPCHKSUMENABLE 0 #define R_CAM4X128TABLE 0x172 -#define O_CAM4X128TABLE__ClassId 7 -#define W_CAM4X128TABLE__ClassId 2 -#define O_CAM4X128TABLE__BucketId 1 -#define W_CAM4X128TABLE__BucketId 6 -#define O_CAM4X128TABLE__UseBucket 0 +#define O_CAM4X128TABLE__CLASSID 7 +#define W_CAM4X128TABLE__CLASSID 2 +#define O_CAM4X128TABLE__BUCKETID 1 +#define W_CAM4X128TABLE__BUCKETID 6 +#define O_CAM4X128TABLE__USEBUCKET 0 #define R_CAM4X128KEY 0x180 #define R_TRANSLATETABLE 0x1A0 #define R_DMACR0 0x200 -#define O_DMACR0__Data0WrMaxCr 27 -#define W_DMACR0__Data0WrMaxCr 3 -#define O_DMACR0__Data0RdMaxCr 24 -#define W_DMACR0__Data0RdMaxCr 3 -#define O_DMACR0__Data1WrMaxCr 21 -#define W_DMACR0__Data1WrMaxCr 3 -#define O_DMACR0__Data1RdMaxCr 18 -#define W_DMACR0__Data1RdMaxCr 3 -#define O_DMACR0__Data2WrMaxCr 15 -#define W_DMACR0__Data2WrMaxCr 3 -#define O_DMACR0__Data2RdMaxCr 12 -#define W_DMACR0__Data2RdMaxCr 3 -#define O_DMACR0__Data3WrMaxCr 9 -#define W_DMACR0__Data3WrMaxCr 3 -#define O_DMACR0__Data3RdMaxCr 6 -#define W_DMACR0__Data3RdMaxCr 3 -#define O_DMACR0__Data4WrMaxCr 3 -#define W_DMACR0__Data4WrMaxCr 3 -#define O_DMACR0__Data4RdMaxCr 0 -#define W_DMACR0__Data4RdMaxCr 3 +#define O_DMACR0__DATA0WRMAXCR 27 +#define W_DMACR0__DATA0WRMAXCR 3 +#define O_DMACR0__DATA0RDMAXCR 24 +#define W_DMACR0__DATA0RDMAXCR 3 +#define O_DMACR0__DATA1WRMAXCR 21 +#define W_DMACR0__DATA1WRMAXCR 3 +#define O_DMACR0__DATA1RDMAXCR 18 +#define W_DMACR0__DATA1RDMAXCR 3 +#define O_DMACR0__DATA2WRMAXCR 15 +#define W_DMACR0__DATA2WRMAXCR 3 +#define O_DMACR0__DATA2RDMAXCR 12 +#define W_DMACR0__DATA2RDMAXCR 3 +#define O_DMACR0__DATA3WRMAXCR 9 +#define W_DMACR0__DATA3WRMAXCR 3 +#define O_DMACR0__DATA3RDMAXCR 6 +#define W_DMACR0__DATA3RDMAXCR 3 +#define O_DMACR0__DATA4WRMAXCR 3 +#define W_DMACR0__DATA4WRMAXCR 3 +#define O_DMACR0__DATA4RDMAXCR 0 +#define W_DMACR0__DATA4RDMAXCR 3 #define R_DMACR1 0x201 -#define O_DMACR1__Data5WrMaxCr 27 -#define W_DMACR1__Data5WrMaxCr 3 -#define O_DMACR1__Data5RdMaxCr 24 -#define W_DMACR1__Data5RdMaxCr 3 -#define O_DMACR1__Data6WrMaxCr 21 -#define W_DMACR1__Data6WrMaxCr 3 -#define O_DMACR1__Data6RdMaxCr 18 -#define W_DMACR1__Data6RdMaxCr 3 -#define O_DMACR1__Data7WrMaxCr 15 -#define W_DMACR1__Data7WrMaxCr 3 -#define O_DMACR1__Data7RdMaxCr 12 -#define W_DMACR1__Data7RdMaxCr 3 -#define O_DMACR1__Data8WrMaxCr 9 -#define W_DMACR1__Data8WrMaxCr 3 -#define O_DMACR1__Data8RdMaxCr 6 -#define W_DMACR1__Data8RdMaxCr 3 -#define O_DMACR1__Data9WrMaxCr 3 -#define W_DMACR1__Data9WrMaxCr 3 -#define O_DMACR1__Data9RdMaxCr 0 -#define W_DMACR1__Data9RdMaxCr 3 +#define O_DMACR1__DATA5WRMAXCR 27 +#define W_DMACR1__DATA5WRMAXCR 3 +#define O_DMACR1__DATA5RDMAXCR 24 +#define W_DMACR1__DATA5RDMAXCR 3 +#define O_DMACR1__DATA6WRMAXCR 21 +#define W_DMACR1__DATA6WRMAXCR 3 +#define O_DMACR1__DATA6RDMAXCR 18 +#define W_DMACR1__DATA6RDMAXCR 3 +#define O_DMACR1__DATA7WRMAXCR 15 +#define W_DMACR1__DATA7WRMAXCR 3 +#define O_DMACR1__DATA7RDMAXCR 12 +#define W_DMACR1__DATA7RDMAXCR 3 +#define O_DMACR1__DATA8WRMAXCR 9 +#define W_DMACR1__DATA8WRMAXCR 3 +#define O_DMACR1__DATA8RDMAXCR 6 +#define W_DMACR1__DATA8RDMAXCR 3 +#define O_DMACR1__DATA9WRMAXCR 3 +#define W_DMACR1__DATA9WRMAXCR 3 +#define O_DMACR1__DATA9RDMAXCR 0 +#define W_DMACR1__DATA9RDMAXCR 3 #define R_DMACR2 0x202 -#define O_DMACR2__Data10WrMaxCr 27 -#define W_DMACR2__Data10WrMaxCr 3 -#define O_DMACR2__Data10RdMaxCr 24 -#define W_DMACR2__Data10RdMaxCr 3 -#define O_DMACR2__Data11WrMaxCr 21 -#define W_DMACR2__Data11WrMaxCr 3 -#define O_DMACR2__Data11RdMaxCr 18 -#define W_DMACR2__Data11RdMaxCr 3 -#define O_DMACR2__Data12WrMaxCr 15 -#define W_DMACR2__Data12WrMaxCr 3 -#define O_DMACR2__Data12RdMaxCr 12 -#define W_DMACR2__Data12RdMaxCr 3 -#define O_DMACR2__Data13WrMaxCr 9 -#define W_DMACR2__Data13WrMaxCr 3 -#define O_DMACR2__Data13RdMaxCr 6 -#define W_DMACR2__Data13RdMaxCr 3 -#define O_DMACR2__Data14WrMaxCr 3 -#define W_DMACR2__Data14WrMaxCr 3 -#define O_DMACR2__Data14RdMaxCr 0 -#define W_DMACR2__Data14RdMaxCr 3 +#define O_DMACR2__DATA10WRMAXCR 27 +#define W_DMACR2__DATA10WRMAXCR 3 +#define O_DMACR2__DATA10RDMAXCR 24 +#define W_DMACR2__DATA10RDMAXCR 3 +#define O_DMACR2__DATA11WRMAXCR 21 +#define W_DMACR2__DATA11WRMAXCR 3 +#define O_DMACR2__DATA11RDMAXCR 18 +#define W_DMACR2__DATA11RDMAXCR 3 +#define O_DMACR2__DATA12WRMAXCR 15 +#define W_DMACR2__DATA12WRMAXCR 3 +#define O_DMACR2__DATA12RDMAXCR 12 +#define W_DMACR2__DATA12RDMAXCR 3 +#define O_DMACR2__DATA13WRMAXCR 9 +#define W_DMACR2__DATA13WRMAXCR 3 +#define O_DMACR2__DATA13RDMAXCR 6 +#define W_DMACR2__DATA13RDMAXCR 3 +#define O_DMACR2__DATA14WRMAXCR 3 +#define W_DMACR2__DATA14WRMAXCR 3 +#define O_DMACR2__DATA14RDMAXCR 0 +#define W_DMACR2__DATA14RDMAXCR 3 #define R_DMACR3 0x203 -#define O_DMACR3__Data15WrMaxCr 27 -#define W_DMACR3__Data15WrMaxCr 3 -#define O_DMACR3__Data15RdMaxCr 24 -#define W_DMACR3__Data15RdMaxCr 3 -#define O_DMACR3__SpClassWrMaxCr 21 -#define W_DMACR3__SpClassWrMaxCr 3 -#define O_DMACR3__SpClassRdMaxCr 18 -#define W_DMACR3__SpClassRdMaxCr 3 -#define O_DMACR3__JumFrInWrMaxCr 15 -#define W_DMACR3__JumFrInWrMaxCr 3 -#define O_DMACR3__JumFrInRdMaxCr 12 -#define W_DMACR3__JumFrInRdMaxCr 3 -#define O_DMACR3__RegFrInWrMaxCr 9 -#define W_DMACR3__RegFrInWrMaxCr 3 -#define O_DMACR3__RegFrInRdMaxCr 6 -#define W_DMACR3__RegFrInRdMaxCr 3 -#define O_DMACR3__FrOutWrMaxCr 3 -#define W_DMACR3__FrOutWrMaxCr 3 -#define O_DMACR3__FrOutRdMaxCr 0 -#define W_DMACR3__FrOutRdMaxCr 3 +#define O_DMACR3__DATA15WRMAXCR 27 +#define W_DMACR3__DATA15WRMAXCR 3 +#define O_DMACR3__DATA15RDMAXCR 24 +#define W_DMACR3__DATA15RDMAXCR 3 +#define O_DMACR3__SPCLASSWRMAXCR 21 +#define W_DMACR3__SPCLASSWRMAXCR 3 +#define O_DMACR3__SPCLASSRDMAXCR 18 +#define W_DMACR3__SPCLASSRDMAXCR 3 +#define O_DMACR3__JUMFRINWRMAXCR 15 +#define W_DMACR3__JUMFRINWRMAXCR 3 +#define O_DMACR3__JUMFRINRDMAXCR 12 +#define W_DMACR3__JUMFRINRDMAXCR 3 +#define O_DMACR3__REGFRINWRMAXCR 9 +#define W_DMACR3__REGFRINWRMAXCR 3 +#define O_DMACR3__REGFRINRDMAXCR 6 +#define W_DMACR3__REGFRINRDMAXCR 3 +#define O_DMACR3__FROUTWRMAXCR 3 +#define W_DMACR3__FROUTWRMAXCR 3 +#define O_DMACR3__FROUTRDMAXCR 0 +#define W_DMACR3__FROUTRDMAXCR 3 #define R_REG_FRIN_SPILL_MEM_START_0 0x204 -#define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0 -#define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32 +#define O_REG_FRIN_SPILL_MEM_START_0__REGFRINSPILLMEMSTART0 0 +#define W_REG_FRIN_SPILL_MEM_START_0__REGFRINSPILLMEMSTART0 32 #define R_REG_FRIN_SPILL_MEM_START_1 0x205 -#define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0 -#define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3 +#define O_REG_FRIN_SPILL_MEM_START_1__REGFRINSPILLMEMSTART1 0 +#define W_REG_FRIN_SPILL_MEM_START_1__REGFRINSPILLMEMSTART1 3 #define R_REG_FRIN_SPILL_MEM_SIZE 0x206 -#define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0 -#define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32 +#define O_REG_FRIN_SPILL_MEM_SIZE__REGFRINSPILLMEMSIZE 0 +#define W_REG_FRIN_SPILL_MEM_SIZE__REGFRINSPILLMEMSIZE 32 #define R_FROUT_SPILL_MEM_START_0 0x207 -#define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0 -#define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32 +#define O_FROUT_SPILL_MEM_START_0__FROUTSPILLMEMSTART0 0 +#define W_FROUT_SPILL_MEM_START_0__FROUTSPILLMEMSTART0 32 #define R_FROUT_SPILL_MEM_START_1 0x208 -#define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0 -#define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3 +#define O_FROUT_SPILL_MEM_START_1__FROUTSPILLMEMSTART1 0 +#define W_FROUT_SPILL_MEM_START_1__FROUTSPILLMEMSTART1 3 #define R_FROUT_SPILL_MEM_SIZE 0x209 -#define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0 -#define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32 +#define O_FROUT_SPILL_MEM_SIZE__FROUTSPILLMEMSIZE 0 +#define W_FROUT_SPILL_MEM_SIZE__FROUTSPILLMEMSIZE 32 #define R_CLASS0_SPILL_MEM_START_0 0x20A -#define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0 -#define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32 +#define O_CLASS0_SPILL_MEM_START_0__CLASS0SPILLMEMSTART0 0 +#define W_CLASS0_SPILL_MEM_START_0__CLASS0SPILLMEMSTART0 32 #define R_CLASS0_SPILL_MEM_START_1 0x20B -#define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0 -#define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3 +#define O_CLASS0_SPILL_MEM_START_1__CLASS0SPILLMEMSTART1 0 +#define W_CLASS0_SPILL_MEM_START_1__CLASS0SPILLMEMSTART1 3 #define R_CLASS0_SPILL_MEM_SIZE 0x20C -#define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0 -#define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32 |