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| author | Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> | 2024-05-14 11:45:07 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-08-03 08:48:52 +0200 |
| commit | c775eec144eba0210e83d52863c782e0ee86d7a7 (patch) | |
| tree | 5472233363e17cee74c0df24d280ac7bcc4ef600 /drivers | |
| parent | 4a0a49a89824c058b643361bc8001917c076543a (diff) | |
| download | linux-c775eec144eba0210e83d52863c782e0ee86d7a7.tar.gz linux-c775eec144eba0210e83d52863c782e0ee86d7a7.tar.bz2 linux-c775eec144eba0210e83d52863c782e0ee86d7a7.zip | |
spi: spi-microchip-core: Fix the number of chip selects supported
[ Upstream commit a7ed3a11202d90939a3d00ffcc8cf50703cb7b35 ]
The SPI "hard" controller in PolarFire SoC has eight CS lines, but only
one CS line is wired. When the 'num-cs' property is not specified in
the device tree, the driver defaults to the MAX_CS value, which has
been fixed to 1 to match the hardware configuration; however, when the
'num-cs' property is explicitly defined in the device tree, it
overrides the default value.
Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers")
Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://msgid.link/r/20240514104508.938448-3-prajna.rajendrakumar@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/spi-microchip-core.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c index d352844c798c..d4c08d366874 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -21,7 +21,7 @@ #include <linux/spi/spi.h> #define MAX_LEN (0xffff) -#define MAX_CS (8) +#define MAX_CS (1) #define DEFAULT_FRAMESIZE (8) #define FIFO_DEPTH (32) #define CLK_GEN_MODE1_MAX (255) |