Merge tag 'sound-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound updates from Takashi Iwai:
 "At this time, it's an interesting mixture of changes for both old and
  new stuff. Majority of changes are about ASoC (lots of systematic
  changes for converting remove callbacks to void, and cleanups), while
  we got the fixes and the enhancements of very old PCI cards, too.

  Here are some highlights:

  ALSA/ASoC Core:
   - Continued effort of more ASoC core cleanups
   - Minor improvements for XRUN handling in indirect PCM helpers
   - Code refactoring of PCM core code

  ASoC:
   - Continued feature and simplification work on SOF, including
     addition of a no-DSP mode for bringup, HDA MLink and extensions to
     the IPC4 protocol
   - Hibernation support for CS35L45
   - More DT binding conversions
   - Support for Cirrus Logic CS35L56, Freescale QMC, Maxim MAX98363,
     nVidia systems with MAX9809x and RT5631, Realtek RT712, Renesas
     R-Car Gen4, Rockchip RK3588 and TI TAS5733

  ALSA:
   - Lots of works for legacy emu10k1 and ymfpci PCI drivers
   - PCM kselftest fixes and enhancements"

* tag 'sound-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (586 commits)
  ALSA: emu10k1: use high-level I/O in set_filterQ()
  ALSA: emu10k1: use high-level I/O functions also during init
  ALSA: emu10k1: fix error handling in snd_audigy_i2c_volume_put()
  ALSA: emu10k1: don't stop DSP in _snd_emu10k1_{,audigy_}init_efx()
  ALSA: emu10k1: fix SNDRV_EMU10K1_IOCTL_SINGLE_STEP
  ALSA: emu10k1: skip Sound Blaster-specific hacks for E-MU cards
  ALSA: emu10k1: fixup DSP defines
  ALSA: emu10k1: pull in some register definitions from kX-project
  ALSA: emu10k1: remove some bogus defines
  ALSA: emu10k1: eliminate some unused defines
  ALSA: emu10k1: fix lineup of EMU_HANA_* defines
  ALSA: emu10k1: comment updates
  ALSA: emu10k1: fix snd_emu1010_fpga_read() input masking for rev2 cards
  ALSA: emu10k1: remove unused emu->pcm_playback_efx_substream field
  ALSA: emu10k1: remove unused `resume` parameter from snd_emu10k1_init()
  ALSA: emu10k1: minor optimizations
  ALSA: emu10k1: remove remaining cruft from snd_emu10k1_emu1010_init()
  ALSA: emu10k1: remove apparently pointless EMU_HANA_OPTION_CARDS reads
  ALSA: emu10k1: remove apparently pointless FPGA reads
  ALSA: emu10k1: stop doing weird things with HCFG in snd_emu10k1_emu1010_init()
  ...

23 files changed, 1297 insertions, 496 deletions

diff --git a/include/dt-bindings/soc/cpm1-fsl,tsa.h b/include/dt-bindings/soc/cpm1-fsl,tsa.h
new file mode 100644
index 000000000000..2cc44e867dbe
--- /dev/null
+++ b/include/dt-bindings/soc/cpm1-fsl,tsa.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+
+#ifndef __DT_BINDINGS_SOC_FSL_TSA_H
+#define __DT_BINDINGS_SOC_FSL_TSA_H
+
+#define FSL_CPM_TSA_NU		0	/* Pseuso Cell Id for not used item */
+#define FSL_CPM_TSA_SCC2	1
+#define FSL_CPM_TSA_SCC3	2
+#define FSL_CPM_TSA_SCC4	3
+#define FSL_CPM_TSA_SMC1	4
+#define FSL_CPM_TSA_SMC2	5
+
+#endif
diff --git a/include/dt-bindings/sound/cs35l45.h b/include/dt-bindings/sound/cs35l45.h
index 076da4b2c28d..25386af18445 100644
--- a/include/dt-bindings/sound/cs35l45.h
+++ b/include/dt-bindings/sound/cs35l45.h
@@ -17,4 +17,61 @@
 #define CS35L45_ASP_TX_HIZ_UNUSED	0x1
 #define CS35L45_ASP_TX_HIZ_DISABLED	0x2
 
+/*
+ * Optional GPIOX Sub-nodes:
+ *  The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
+ *  sub-nodes for configuring the GPIO pins.
+ *
+ * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
+ *   is 1.
+ *    0 = Output
+ *    1 = Input (Default)
+ *
+ * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
+ *
+ *    0 = Low (Default)
+ *    1 = High
+ *
+ * - gpio-op-cfg : GPIO output configuration. Valid only when 'gpio-ctrl' is 1
+ *   and 'gpio-dir' is 0.
+ *
+ *    0 = CMOS (Default)
+ *    1 = Open Drain
+ *
+ * - gpio-pol : GPIO output polarity select. Valid only when 'gpio-ctrl' is 1
+ *   and 'gpio-dir' is 0.
+ *
+ *    0 = Non-inverted, Active High (Default)
+ *    1 = Inverted, Active Low
+ *
+ * - gpio-invert : Defines the polarity of the GPIO pin if configured
+ *   as input.
+ *
+ *    0 = Not inverted (Default)
+ *    1 = Inverted
+ *
+ * - gpio-ctrl : Defines the function of the GPIO pin.
+ *
+ * GPIO1:
+ *   0 = High impedance input (Default)
+ *   1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
+ *   2 = Pin acts as MDSYNC, direction controlled by MDSYNC
+ *   3-7 = Reserved
+ *
+ * GPIO2:
+ *   0 = High impedance input (Default)
+ *   1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
+ *   2 = Pin acts as open drain INT
+ *   3 = Reserved
+ *   4 = Pin acts as push-pull output INT. Active low.
+ *   5 = Pin acts as push-pull output INT. Active high.
+ *   6,7 = Reserved
+ *
+ * GPIO3:
+ *   0 = High impedance input (Default)
+ *   1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
+ *   2-7 = Reserved
+ */
+#define CS35L45_NUM_GPIOS	0x3
+
 #endif /* DT_CS35L45_H */
diff --git a/include/linux/firmware/cirrus/cs_dsp.h b/include/linux/firmware/cirrus/cs_dsp.h
index cad828e21c72..29cd11d5a3cf 100644
--- a/include/linux/firmware/cirrus/cs_dsp.h
+++ b/include/linux/firmware/cirrus/cs_dsp.h
@@ -156,6 +156,7 @@ struct cs_dsp {
 	unsigned int sysclk_reg;
 	unsigned int sysclk_mask;
 	unsigned int sysclk_shift;
+	bool no_core_startstop;
 
 	struct list_head alg_regions;
 
diff --git a/include/soc/fsl/qe/qmc.h b/include/soc/fsl/qe/qmc.h
new file mode 100644
index 000000000000..3c61a50d2ae2
--- /dev/null
+++ b/include/soc/fsl/qe/qmc.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QMC management
+ *
+ * Copyright 2022 CS GROUP France
+ *
+ * Author: Herve Codina <herve.codina@bootlin.com>
+ */
+#ifndef __SOC_FSL_QMC_H__
+#define __SOC_FSL_QMC_H__
+
+#include <linux/types.h>
+
+struct device_node;
+struct device;
+struct qmc_chan;
+
+struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char *phandle_name);
+void qmc_chan_put(struct qmc_chan *chan);
+struct qmc_chan *devm_qmc_chan_get_byphandle(struct device *dev, struct device_node *np,
+					     const char *phandle_name);
+
+enum qmc_mode {
+	QMC_TRANSPARENT,
+	QMC_HDLC,
+};
+
+struct qmc_chan_info {
+	enum qmc_mode mode;
+	unsigned long rx_fs_rate;
+	unsigned long rx_bit_rate;
+	u8 nb_rx_ts;
+	unsigned long tx_fs_rate;
+	unsigned long tx_bit_rate;
+	u8 nb_tx_ts;
+};
+
+int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info);
+
+struct qmc_chan_param {
+	enum qmc_mode mode;
+	union {
+		struct {
+			u16 max_rx_buf_size;
+			u16 max_rx_frame_size;
+			bool is_crc32;
+		} hdlc;
+		struct {
+			u16 max_rx_buf_size;
+		} transp;
+	};
+};
+
+int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param);
+
+int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
+			  void (*complete)(void *context), void *context);
+
+int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
+			 void (*complete)(void *context, size_t length),
+			 void *context);
+
+#define QMC_CHAN_READ  (1<<0)
+#define QMC_CHAN_WRITE (1<<1)
+#define QMC_CHAN_ALL   (QMC_CHAN_READ | QMC_CHAN_WRITE)
+
+int qmc_chan_start(struct qmc_chan *chan, int direction);
+int qmc_chan_stop(struct qmc_chan *chan, int direction);
+int qmc_chan_reset(struct qmc_chan *chan, int direction);
+
+#endif /* __SOC_FSL_QMC_H__ */
diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h
index 49200ec26dc4..c495c6d5fbe0 100644
--- a/include/sound/ac97_codec.h
+++ b/include/sound/ac97_codec.h
@@ -335,6 +335,9 @@ static inline int snd_ac97_update_power(struct snd_ac97 *ac97, int reg,
 #ifdef CONFIG_PM
 void snd_ac97_suspend(struct snd_ac97 *ac97);
 void snd_ac97_resume(struct snd_ac97 *ac97);
+#else
+static inline void snd_ac97_suspend(struct snd_ac97 *ac97) {}
+static inline void snd_ac97_resume(struct snd_ac97 *ac97) {}
 #endif
 int snd_ac97_reset(struct snd_ac97 *ac97, bool try_warm, unsigned int id,
 	unsigned int id_mask);
diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h
index 9ac5918269a5..7239d943942c 100644
--- a/include/sound/cs35l41.h
+++ b/include/sound/cs35l41.h
@@ -11,6 +11,7 @@
 #define __CS35L41_H
 
 #include <linux/regmap.h>
+#include <linux/completion.h>
 #include <linux/firmware/cirrus/cs_dsp.h>
 
 #define CS35L41_FIRSTREG		0x00000000
@@ -677,6 +678,7 @@
 
 #define CS35L36_PUP_DONE_IRQ_UNMASK	0x5F
 #define CS35L36_PUP_DONE_IRQ_MASK	0xBF
+#define CS35L41_SYNC_EN_MASK		BIT(8)
 
 #define CS35L41_AMP_SHORT_ERR		0x80000000
 #define CS35L41_BST_SHORT_ERR		0x0100
@@ -686,6 +688,7 @@
 #define CS35L41_BST_DCM_UVP_ERR		0x80
 #define CS35L41_OTP_BOOT_DONE		0x02
 #define CS35L41_PLL_UNLOCK		0x10
+#define CS35L41_PLL_LOCK		BIT(1)
 #define CS35L41_OTP_BOOT_ERR		0x80000000
 
 #define CS35L41_AMP_SHORT_ERR_RLS	0x02
@@ -705,6 +708,8 @@
 #define CS35L41_INT1_MASK_DEFAULT	0x7FFCFE3F
 #define CS35L41_INT1_UNMASK_PUP		0xFEFFFFFF
 #define CS35L41_INT1_UNMASK_PDN		0xFF7FFFFF
+#define CS35L41_INT3_PLL_LOCK_SHIFT	1
+#define CS35L41_INT3_PLL_LOCK_MASK	BIT(CS35L41_INT3_PLL_LOCK_SHIFT)
 
 #define CS35L41_GPIO_DIR_MASK		0x80000000
 #define CS35L41_GPIO_DIR_SHIFT		31
@@ -742,6 +747,11 @@
 enum cs35l41_boost_type {
 	CS35L41_INT_BOOST,
 	CS35L41_EXT_BOOST,
+	CS35L41_SHD_BOOST_ACTV,
+	CS35L41_SHD_BOOST_PASS,
+
+	// Not present in Binding Documentation, so no system should use this value.
+	// This value is only used in CLSA0100 Laptop
 	CS35L41_EXT_BOOST_NO_VSPK_SWITCH,
 };
 
@@ -891,6 +901,7 @@ int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap);
 int cs35l41_init_boost(struct device *dev, struct regmap *regmap,
 		       struct cs35l41_hw_cfg *hw_cfg);
 bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type);
-int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable);
+int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable,
+			  struct completion *pll_lock);
 
 #endif /* __CS35L41_H */
diff --git a/include/sound/cs35l56.h b/include/sound/cs35l56.h
new file mode 100644
index 000000000000..002042b1c73c
--- /dev/null
+++ b/include/sound/cs35l56.h
@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Common definitions for Cirrus Logic CS35L56 smart amp
+ *
+ * Copyright (C) 2023 Cirrus Logic, Inc. and
+ *                    Cirrus Logic International Semiconductor Ltd.
+ */
+
+#ifndef __CS35L56_H
+#define __CS35L56_H
+
+#include <linux/firmware/cirrus/cs_dsp.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regmap.h>
+
+#define CS35L56_DEVID					0x0000000
+#define CS35L56_REVID					0x0000004
+#define CS35L56_RELID					0x000000C
+#define CS35L56_OTPID					0x0000010
+#define CS35L56_SFT_RESET				0x0000020
+#define CS35L56_GLOBAL_ENABLES				0x0002014
+#define CS35L56_BLOCK_ENABLES				0x0002018
+#define CS35L56_BLOCK_ENABLES2				0x000201C
+#define CS35L56_REFCLK_INPUT				0x0002C04
+#define CS35L56_GLOBAL_SAMPLE_RATE			0x0002C0C
+#define CS35L56_ASP1_ENABLES1				0x0004800
+#define CS35L56_ASP1_CONTROL1				0x0004804
+#define CS35L56_ASP1_CONTROL2				0x0004808
+#define CS35L56_ASP1_CONTROL3				0x000480C
+#define CS35L56_ASP1_FRAME_CONTROL1			0x0004810
+#define CS35L56_ASP1_FRAME_CONTROL5			0x0004820
+#define CS35L56_ASP1_DATA_CONTROL1			0x0004830
+#define CS35L56_ASP1_DATA_CONTROL5			0x0004840
+#define CS35L56_DACPCM1_INPUT				0x0004C00
+#define CS35L56_DACPCM2_INPUT				0x0004C08
+#define CS35L56_ASP1TX1_INPUT				0x0004C20
+#define CS35L56_ASP1TX2_INPUT				0x0004C24
+#define CS35L56_ASP1TX3_INPUT				0x0004C28
+#define CS35L56_ASP1TX4_INPUT				0x0004C2C
+#define CS35L56_DSP1RX1_INPUT				0x0004C40
+#define CS35L56_DSP1RX2_INPUT				0x0004C44
+#define CS35L56_SWIRE_DP3_CH1_INPUT			0x0004C70
+#define CS35L56_SWIRE_DP3_CH2_INPUT			0x0004C74
+#define CS35L56_SWIRE_DP3_CH3_INPUT			0x0004C78
+#define CS35L56_SWIRE_DP3_CH4_INPUT			0x0004C7C
+#define CS35L56_IRQ1_CFG				0x000E000
+#define CS35L56_IRQ1_STATUS				0x000E004
+#define CS35L56_IRQ1_EINT_1				0x000E010
+#define CS35L56_IRQ1_EINT_2				0x000E014
+#define CS35L56_IRQ1_EINT_4				0x000E01C
+#define CS35L56_IRQ1_EINT_8				0x000E02C
+#define CS35L56_IRQ1_EINT_18				0x000E054
+#define CS35L56_IRQ1_EINT_20				0x000E05C
+#define CS35L56_IRQ1_MASK_1				0x000E090
+#define CS35L56_IRQ1_MASK_2				0x000E094
+#define CS35L56_IRQ1_MASK_4				0x000E09C
+#define CS35L56_IRQ1_MASK_8				0x000E0AC
+#define CS35L56_IRQ1_MASK_18				0x000E0D4
+#define CS35L56_IRQ1_MASK_20				0x000E0DC
+#define CS35L56_DSP_VIRTUAL1_MBOX_1			0x0011020
+#define CS35L56_DSP_VIRTUAL1_MBOX_2			0x0011024
+#define CS35L56_DSP_VIRTUAL1_MBOX_3			0x0011028
+#define CS35L56_DSP_VIRTUAL1_MBOX_4			0x001102C
+#define CS35L56_DSP_VIRTUAL1_MBOX_5			0x0011030
+#define CS35L56_DSP_VIRTUAL1_MBOX_6			0x0011034
+#define CS35L56_DSP_VIRTUAL1_MBOX_7			0x0011038
+#define CS35L56_DSP_VIRTUAL1_MBOX_8			0x001103C
+#define CS35L56_DSP_RESTRICT_STS1			0x00190F0
+#define CS35L56_DSP1_XMEM_PACKED_0			0x2000000
+#define CS35L56_DSP1_XMEM_PACKED_6143			0x2005FFC
+#define CS35L56_DSP1_XMEM_UNPACKED32_0			0x2400000
+#define CS35L56_DSP1_XMEM_UNPACKED32_4095		0x2403FFC
+#define CS35L56_DSP1_SYS_INFO_ID			0x25E0000
+#define CS35L56_DSP1_SYS_INFO_END			0x25E004C
+#define CS35L56_DSP1_AHBM_WINDOW_DEBUG_0		0x25E2040
+#define CS35L56_DSP1_AHBM_WINDOW_DEBUG_1		0x25E2044
+#define CS35L56_DSP1_XMEM_UNPACKED24_0			0x2800000
+#define CS35L56_DSP1_HALO_STATE_A1			0x2801E58
+#define CS35L56_DSP1_HALO_STATE				0x28021E0
+#define CS35L56_DSP1_PM_CUR_STATE_A1			0x2804000
+#define CS35L56_DSP1_PM_CUR_STATE			0x2804308
+#define CS35L56_DSP1_XMEM_UNPACKED24_8191		0x2807FFC
+#define CS35L56_DSP1_CORE_BASE				0x2B80000
+#define CS35L56_DSP1_SCRATCH1				0x2B805C0
+#define CS35L56_DSP1_SCRATCH2				0x2B805C8
+#define CS35L56_DSP1_SCRATCH3				0x2B805D0
+#define CS35L56_DSP1_SCRATCH4				0x2B805D8
+#define CS35L56_DSP1_YMEM_PACKED_0			0x2C00000
+#define CS35L56_DSP1_YMEM_PACKED_4604			0x2C047F0
+#define CS35L56_DSP1_YMEM_UNPACKED32_0			0x3000000
+#define CS35L56_DSP1_YMEM_UNPACKED32_3070		0x3002FF8
+#define CS35L56_DSP1_YMEM_UNPACKED24_0			0x3400000
+#define CS35L56_MAIN_RENDER_USER_MUTE			0x3400024
+#define CS35L56_MAIN_RENDER_USER_VOLUME			0x340002C
+#define CS35L56_MAIN_POSTURE_NUMBER			0x3400094
+#define CS35L56_PROTECTION_STATUS			0x34000D8
+#define CS35L56_TRANSDUCER_ACTUAL_PS			0x3400150
+#define CS35L56_DSP1_YMEM_UNPACKED24_6141		0x3405FF4
+#define CS35L56_DSP1_PMEM_0				0x3800000
+#define CS35L56_DSP1_PMEM_5114				0x3804FE8
+
+/* DEVID */
+#define CS35L56_DEVID_MASK				0x00FFFFFF
+
+/* REVID */
+#define CS35L56_AREVID_MASK				0x000000F0
+#define CS35L56_MTLREVID_MASK				0x0000000F
+#define CS35L56_REVID_B0				0x000000B0
+
+/* ASP_ENABLES1 */
+#define CS35L56_ASP_RX2_EN_SHIFT			17
+#define CS35L56_ASP_RX1_EN_SHIFT			16
+#define CS35L56_ASP_TX4_EN_SHIFT			3
+#define CS35L56_ASP_TX3_EN_SHIFT			2
+#define CS35L56_ASP_TX2_EN_SHIFT			1
+#define CS35L56_ASP_TX1_EN_SHIFT			0
+
+/* ASP_CONTROL1 */
+#define CS35L56_ASP_BCLK_FREQ_MASK			0x0000003F
+#define CS35L56_ASP_BCLK_FREQ_SHIFT			0
+
+/* ASP_CONTROL2 */
+#define CS35L56_ASP_RX_WIDTH_MASK			0xFF000000
+#define CS35L56_ASP_RX_WIDTH_SHIFT			24
+#define CS35L56_ASP_TX_WIDTH_MASK			0x00FF0000
+#define CS35L56_ASP_TX_WIDTH_SHIFT			16
+#define CS35L56_ASP_FMT_MASK				0x00000700
+#define CS35L56_ASP_FMT_SHIFT				8
+#define CS35L56_ASP_BCLK_INV_MASK			0x00000040
+#define CS35L56_ASP_FSYNC_INV_MASK			0x00000004
+
+/* ASP_CONTROL3 */
+#define CS35L56_ASP1_DOUT_HIZ_CTRL_MASK			0x00000003
+
+/* ASP_DATA_CONTROL1 */
+#define CS35L56_ASP_TX_WL_MASK				0x0000003F
+
+/* ASP_DATA_CONTROL5 */
+#define CS35L56_ASP_RX_WL_MASK				0x0000003F
+
+/* ASPTXn_INPUT */
+#define CS35L56_ASP_TXn_SRC_MASK			0x0000007F
+
+/* SWIRETX[1..7]_SRC SDWTXn INPUT */
+#define CS35L56_SWIRETXn_SRC_MASK			0x0000007F
+
+/* IRQ1_STATUS */
+#define CS35L56_IRQ1_STS_MASK				0x00000001
+
+/* IRQ1_EINT_1 */
+#define CS35L56_AMP_SHORT_ERR_EINT1_MASK		0x80000000
+
+/* IRQ1_EINT_2 */
+#define CS35L56_DSP_VIRTUAL2_MBOX_WR_EINT1_MASK		0x00200000
+
+/* IRQ1_EINT_4 */
+#define CS35L56_OTP_BOOT_DONE_MASK			0x00000002
+
+/* IRQ1_EINT_8 */
+#define CS35L56_TEMP_ERR_EINT1_MASK			0x80000000
+
+/* Mixer input sources */
+#define CS35L56_INPUT_SRC_NONE				0x00
+#define CS35L56_INPUT_SRC_ASP1RX1			0x08
+#define CS35L56_INPUT_SRC_ASP1RX2			0x09
+#define CS35L56_INPUT_SRC_VMON				0x18
+#define CS35L56_INPUT_SRC_IMON				0x19
+#define CS35L56_INPUT_SRC_ERR_VOL			0x20
+#define CS35L56_INPUT_SRC_CLASSH			0x21
+#define CS35L56_INPUT_SRC_VDDBMON			0x28
+#define CS35L56_INPUT_SRC_VBSTMON			0x29
+#define CS35L56_INPUT_SRC_DSP1TX1			0x32
+#define CS35L56_INPUT_SRC_DSP1TX2			0x33
+#define CS35L56_INPUT_SRC_DSP1TX3			0x34
+#define CS35L56_INPUT_SRC_DSP1TX4			0x35
+#define CS35L56_INPUT_SRC_DSP1TX5			0x36
+#define CS35L56_INPUT_SRC_DSP1TX6			0x37
+#define CS35L56_INPUT_SRC_DSP1TX7			0x38
+#define CS35L56_INPUT_SRC_DSP1TX8			0x39
+#define CS35L56_INPUT_SRC_TEMPMON			0x3A
+#define CS35L56_INPUT_SRC_INTERPOLATOR			0x40
+#define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1		0x44
+#define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2		0x45
+#define CS35L56_INPUT_MASK				0x7F
+
+#define CS35L56_NUM_INPUT_SRC				21
+
+/* ASP formats */
+#define CS35L56_ASP_FMT_DSP_A				0
+#define CS35L56_ASP_FMT_I2S				2
+
+/* ASP HiZ modes */
+#define CS35L56_ASP_UNUSED_HIZ_OFF_HIZ			3
+
+/* MAIN_RENDER_ACTUAL_PS */
+#define CS35L56_PS0					0
+#define CS35L56_PS3					3
+
+/* CS35L56_DSP_RESTRICT_STS1 */
+#define CS35L56_RESTRICTED_MASK				0x7
+
+/* CS35L56_MAIN_RENDER_USER_MUTE */
+#define CS35L56_MAIN_RENDER_USER_MUTE_MASK		1
+
+/* CS35L56_MAIN_RENDER_USER_VOLUME */
+#define CS35L56_MAIN_RENDER_USER_VOLUME_MIN		-400
+#define CS35L56_MAIN_RENDER_USER_VOLUME_MAX		400
+#define CS35L56_MAIN_RENDER_USER_VOLUME_MASK		0x0000FFC0
+#define CS35L56_MAIN_RENDER_USER_VOLUME_SHIFT		6
+#define CS35L56_MAIN_RENDER_USER_VOLUME_SIGNBIT		9
+
+/* CS35L56_MAIN_POSTURE_NUMBER */
+#define CS35L56_MAIN_POSTURE_MIN			0
+#define CS35L56_MAIN_POSTURE_MAX			255
+#define CS35L56_MAIN_POSTURE_MASK			CS35L56_MAIN_POSTURE_MAX
+
+/* CS35L56_PROTECTION_STATUS */
+#define CS35L56_FIRMWARE_MISSING			BIT(0)
+
+/* Software Values */
+#define CS35L56_HALO_STATE_SHUTDOWN			1
+#define CS35L56_HALO_STATE_BOOT_DONE			2
+
+#define CS35L56_MBOX_CMD_AUDIO_PLAY			0x0B000001
+#define CS35L56_MBOX_CMD_AUDIO_PAUSE			0x0B000002
+#define CS35L56_MBOX_CMD_HIBERNATE_NOW			0x02000001
+#define CS35L56_MBOX_CMD_WAKEUP				0x02000002
+#define CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE		0x02000003
+#define CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE		0x02000004
+#define CS35L56_MBOX_CMD_SHUTDOWN			0x02000005
+#define CS35L56_MBOX_CMD_SYSTEM_RESET			0x02000007
+
+#define CS35L56_MBOX_TIMEOUT_US				5000
+#define CS35L56_MBOX_POLL_US				250
+
+#define CS35L56_PS0_POLL_US				500
+#define CS35L56_PS0_TIMEOUT_US				50000
+#define CS35L56_PS3_POLL_US				500
+#define CS35L56_PS3_TIMEOUT_US				300000
+
+#define CS35L56_CONTROL_PORT_READY_US			2200
+#define CS35L56_HALO_STATE_POLL_US			1000
+#define CS35L56_HALO_STATE_TIMEOUT_US			50000
+#define CS35L56_HIBERNATE_WAKE_POLL_US			500
+#define CS35L56_HIBERNATE_WAKE_TIMEOUT_US		5000
+#define CS35L56_RESET_PULSE_MIN_US			1100
+
+#define CS35L56_SDW1_PLAYBACK_PORT			1
+#define CS35L56_SDW1_CAPTURE_PORT			3
+
+#define CS35L56_NUM_BULK_SUPPLIES			3
+#define CS35L56_NUM_DSP_REGIONS				5
+
+extern struct regmap_config cs35l56_regmap_i2c;
+extern struct regmap_config cs35l56_regmap_spi;
+extern struct regmap_config cs35l56_regmap_sdw;
+
+extern const struct cs_dsp_region cs35l56_dsp1_regions[CS35L56_NUM_DSP_REGIONS];
+extern const char * const cs35l56_tx_input_texts[CS35L56_NUM_INPUT_SRC];
+extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC];
+
+void cs35l56_reread_firmware_registers(struct device *dev, struct regmap *regmap);
+int cs35l56_get_bclk_freq_id(unsigned int freq);
+void cs35l56_fill_supply_names(struct regulator_bulk_data *data);
+
+#endif /* ifndef __CS35L56_H */
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 39787fecc8d9..8fe80dcee71b 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -25,13 +25,9 @@
 /* ------------------- DEFINES -------------------- */
 
 #define EMUPAGESIZE     4096
-#define MAXREQVOICES    8
 #define MAXPAGES0       4096	/* 32 bit mode */
 #define MAXPAGES1       8192	/* 31 bit mode */
-#define RESERVED        0
-#define NUM_MIDI        16
 #define NUM_G           64              /* use all channels */
-#define NUM_FXSENDS     4
 #define NUM_EFX_PLAYBACK    16
 
 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
@@ -39,7 +35,6 @@
 #define AUDIGY_DMA_MASK		0xffffffffUL	/* 32bit mode */
 
 #define TMEMSIZE        256*1024
-#define TMEMSIZEREG     4
 
 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
 
@@ -66,8 +61,8 @@
 						/* the relevant bits and zero to the other bits	*/
 #define IPR_P16V		0x80000000	/* Bit set when the CA0151 P16V chip wishes
 						   to interrupt */
-#define IPR_GPIOMSG		0x20000000	/* GPIO message interrupt (RE'd, still not sure 
-						   which INTE bits enable it)			*/
+#define IPR_WATERMARK_REACHED	0x40000000
+#define IPR_A_GPIO		0x20000000	/* GPIO input pin change			*/
 
 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1)			*/
 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000	/* MIDI UART transmit buffer empty		*/
@@ -97,9 +92,9 @@
 #define IPR_CHANNELLOOP		0x00000040	/* Channel (half) loop interrupt(s) pending	*/
 #define IPR_CHANNELNUMBERMASK	0x0000003f	/* When IPR_CHANNELLOOP is set, indicates the	*/
 						/* highest set channel in CLIPL, CLIPH, HLIPL,  */
-						/* or HLIPH.  When IP is written with CL set,	*/
+						/* or HLIPH.  When IPR is written with CL set,	*/
 						/* the bit in H/CLIPL or H/CLIPH corresponding	*/
-						/* to the CIN value written will be cleared.	*/
+						/* to the CN value written will be cleared.	*/
 
 #define INTE			0x0c		/* Interrupt enable register			*/
 #define INTE_VIRTUALSB_MASK	0xc0000000	/* Virtual Soundblaster I/O port capture	*/
@@ -127,10 +122,14 @@
 						/* behavior and possibly random segfaults and	*/
 						/* lockups if enabled.				*/
 
+#define INTE_A_GPIOENABLE 	0x00040000	/* Enable GPIO input change interrupts		*/
+
 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1)			*/
 #define INTE_A_MIDITXENABLE2	0x00020000	/* Enable MIDI transmit-buffer-empty interrupts	*/
 #define INTE_A_MIDIRXENABLE2	0x00010000	/* Enable MIDI receive-buffer-empty interrupts	*/
 
+#define INTE_A_SPDIF_BUFFULL_ENABLE 	0x00008000
+#define INTE_A_SPDIF_HALFBUFFULL_ENABLE	0x00004000
 
 #define INTE_SAMPLERATETRACKER	0x00002000	/* Enable sample rate tracker interrupts	*/
 						/* NOTE: This bit must always be enabled       	*/
@@ -151,9 +150,10 @@
 #define WC			0x10		/* Wall Clock register				*/
 #define WC_SAMPLECOUNTER_MASK	0x03FFFFC0	/* Sample periods elapsed since reset		*/
 #define WC_SAMPLECOUNTER	0x14060010
-#define WC_CURRENTCHANNEL	0x0000003F	/* Channel [0..63] currently being serviced	*/
+#define WC_CURRENTCHANNEL_MASK	0x0000003F	/* Channel [0..63] currently being serviced	*/
 						/* NOTE: Each channel takes 1/64th of a sample	*/
 						/* period to be serviced.			*/
+#define WC_CURRENTCHANNEL	0x06000010
 
 #define HCFG			0x14		/* Hardware config register			*/
 						/* NOTE: There is no reason to use the legacy	*/
@@ -180,6 +180,7 @@
 #define HCFG_CODECFORMAT_MASK	0x00030000	/* CODEC format					*/
 
 /* Specific to Alice2, CA0102 */
+
 #define HCFG_CODECFORMAT_AC97_1	0x00000000	/* AC97 CODEC format -- Ver 1.03		*/
 #define HCFG_CODECFORMAT_AC97_2	0x00010000	/* AC97 CODEC format -- Ver 2.1			*/
 #define HCFG_AUTOMUTE_ASYNC	0x00008000	/* When set, the async sample rate convertors	*/
@@ -200,9 +201,8 @@
  						/* I2S format input				*/
 /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc.  */
 
-
-
 /* Older chips */
+
 #define HCFG_CODECFORMAT_AC97	0x00000000	/* AC97 CODEC format -- Primary Output		*/
 #define HCFG_CODECFORMAT_I2S	0x00010000	/* I2S CODEC format -- Secondary (Rear) Output	*/
 #define HCFG_GPINPUT0		0x00004000	/* External pin112				*/
@@ -238,7 +238,7 @@
 						/* Should be set to 1 when the EMU10K1 is	*/
 						/* completely initialized.			*/
 
-//For Audigy, MPU port move to 0x70-0x74 ptr register
+// On Audigy, the MPU port moved to the 0x70-0x74 ptr registers
 
 #define MUDATA			0x18		/* MPU401 data register (8 bits)       		*/
 
@@ -251,11 +251,17 @@
 #define MUSTAT_IRDYN		0x80		/* 0 = MIDI data or command ACK			*/
 #define MUSTAT_ORDYN		0x40		/* 0 = MUDATA can accept a command or data	*/
 
-#define A_IOCFG			0x18		/* GPIO on Audigy card (16bits)			*/
-#define A_GPINPUT_MASK		0xff00
+#define A_GPIO			0x18		/* GPIO on Audigy card (16bits)			*/
+#define A_GPINPUT_MASK		0xff00		/* Alice/2 has 8 input pins			*/
+#define A3_GPINPUT_MASK		0x3f00		/* ... while Tina/2 has only 6			*/
 #define A_GPOUTPUT_MASK		0x00ff
 
+// The GPIO port is used for I/O config on Sound Blasters;
+// card-specific info can be found in the emu_chip_details table.
+// On E-MU cards the port is used as the interface to the FPGA.
+
 // Audigy output/GPIO stuff taken from the kX drivers
+#define A_IOCFG			A_GPIO
 #define A_IOCFG_GPOUT0		0x0044		/* analog/digital				*/
 #define A_IOCFG_DISABLE_ANALOG	0x0040		/* = 'enable' for Audigy2 (chiprev=4)		*/
 #define A_IOCFG_ENABLE_DIGITAL	0x0004
@@ -271,19 +277,12 @@
 #define A_IOCFG_REAR_JACK       0x8000
 #define A_IOCFG_PHONES_JACK     0x0100          /* LiveDrive					*/
 
-/* outputs:
- *	for audigy2 platinum:	0xa00
- *	for a2 platinum ex:	0x1c00
- *	for a1 platinum:	0x0
- */
-
 #define TIMER			0x1a		/* Timer terminal count register		*/
 						/* NOTE: After the rate is changed, a maximum	*/
 						/* of 1024 sample periods should be allowed	*/
 						/* before the new rate is guaranteed accurate.	*/
-#define TIMER_RATE_MASK		0x000003ff	/* Timer interrupt rate in sample periods	*/
+#define TIMER_RATE_MASK		0x03ff		/* Timer interrupt rate in sample periods	*/
 						/* 0 == 1024 periods, [1..4] are not useful	*/
-#define TIMER_RATE		0x0a00001a
 
 #define AC97DATA		0x1c		/* AC97 register set data register (16 bit)	*/
 
@@ -317,7 +316,7 @@
 						/* 0x00000000 2-channel output. */
 						/* 0x00000200 8-channel output. */
 						/* 0x00000004 pauses stream/irq fail. */
-						/* Rest of bits no nothing to sound output */
+						/* Rest of bits do nothing to sound output */
 						/* bit 0: Enable P16V audio.
 						 * bit 1: Lock P16V record memory cache.
 						 * bit 2: Lock P16V playback memory cache.
@@ -331,6 +330,7 @@
 						 */
 #define IPR3			0x38		/* Cdif interrupt pending register		*/
 #define INTE3			0x3c		/* Cdif interrupt enable register. 	*/
+
 /************************************************************************************************/
 /* PCI function 1 registers, address = <val> + PCIBASE1						*/
 /************************************************************************************************/
@@ -349,11 +349,38 @@
 #define JOYSTICK_BUTTONS	0x0f		/* Joystick button data				*/
 #define JOYSTICK_COMPARATOR	0xf0		/* Joystick comparator data			*/
 
-
 /********************************************************************************************************/
 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers			*/
 /********************************************************************************************************/
 
+// No official documentation was released for EMU10K1, but some info
+// about playback can be extrapolated from the EMU8K documents:
+// "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers
+// "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view
+
+// The short version:
+// - The engine has 64 playback channels, also called voices. The channels
+//   operate independently, except when paired for stereo (see below).
+// - PCM samples are fetched into the cache; see description of CD0 below.
+// - Samples are consumed at the rate CPF_CURRENTPITCH.
+// - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8
+// - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated
+//   according to CCCA_INTERPROM_*. With CCCA_INTERPROM_0 selected and a zero
+//   CPF_FRACADDRESS, this results in CCR_READADDRESS[3] being used verbatim.
+// - The value is multiplied by CVCF_CURRENTVOL.
+// - The value goes through a filter with cutoff CVCF_CURRENTFILTER;
+//   delay stages Z1 and Z2.
+// - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2)
+//   of the 16 (EMU10K1) / 64 (EMU10K2) FX bus accumulators via FXRT*,
+//   multiplied by a per-send amount (*_FXSENDAMOUNT_*).
+//   The scaling of the send amounts is exponential-ish.
+// - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*.
+// - The pitch, volume, and filter cutoff can be modulated by two envelope
+//   engines and two low frequency oscillators.
+// - To avoid abrupt changes to the parameters (which may cause audible
+//   distortion), the modulation engine sets the target registers, towards
+//   which the current registers "swerve" gradually.
+
 #define CPF			0x00		/* Current pitch and fraction register			*/
 #define CPF_CURRENTPITCH_MASK	0xffff0000	/* Current pitch (linear, 0x4000 == unity pitch shift) 	*/
 #define CPF_CURRENTPITCH	0x10100000
@@ -393,7 +420,7 @@
 #define PSST_LOOPSTARTADDR_MASK	0x00ffffff	/* Loop start address of the specified channel		*/
 #define PSST_LOOPSTARTADDR	0x18000006
 
-#define DSL			0x07		/* Send D amount and loop start address register	*/
+#define DSL			0x07		/* Send D amount and loop end address register	*/
 #define DSL_FXSENDAMOUNT_D_MASK	0xff000000	/* Linear level of channel output sent to FX send bus D	*/
 
 #define DSL_FXSENDAMOUNT_D	0x08180007
@@ -402,8 +429,9 @@
 #define DSL_LOOPENDADDR		0x18000007
 
 #define CCCA			0x08		/* Filter Q, interp. ROM, byte size, cur. addr register */
-#define CCCA_RESONANCE		0xf0000000	/* Lowpass filter resonance (Q) height			*/
-#define CCCA_INTERPROMMASK	0x0e000000	/* Selects passband of interpolation ROM		*/
+#define CCCA_RESONANCE_MASK	0xf0000000	/* Lowpass filter resonance (Q) height			*/
+#define CCCA_RESONANCE		0x041c0008
+#define CCCA_INTERPROM_MASK	0x0e000000	/* Selects passband of interpolation ROM		*/
 						/* 1 == full band, 7 == lowpass				*/
 						/* ROM 0 is used when pitch shifting downward or less	*/
 						/* then 3 semitones upward.  Increasingly higher ROM	*/
@@ -418,25 +446,28 @@
 #define CCCA_INTERPROM_6	0x0c000000	/* Select interpolation ROM 6				*/
 #define CCCA_INTERPROM_7	0x0e000000	/* Select interpolation ROM 7				*/
 #de