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| author | Dave Airlie <airlied@redhat.com> | 2023-03-03 08:26:59 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2023-03-03 08:26:59 +1000 |
| commit | 54ceb92724a8cf5294c284d5e9f770fc763cdab2 (patch) | |
| tree | 24ad116766b4a21e27c9d86977112f5722a18b06 /include | |
| parent | 7b7d2429a1d2f789f4ce34afadbd76510a0236cc (diff) | |
| parent | 6bb811d0ee3e1fe9f22a028c89b3472c999b70bc (diff) | |
| download | linux-54ceb92724a8cf5294c284d5e9f770fc763cdab2.tar.gz linux-54ceb92724a8cf5294c284d5e9f770fc763cdab2.tar.bz2 linux-54ceb92724a8cf5294c284d5e9f770fc763cdab2.zip | |
Merge tag 'amd-drm-fixes-6.3-2023-03-02' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-fixes-6.3-2023-03-02:
amdgpu:
- SMU 13 fixes
- Enable TMZ for GC 10.3.6
- Misc display fixes
- Buddy allocator fixes
- GC 11 fixes
- S0ix fix
- INFO IOCTL queries for GC 11
- VCN harvest fixes for SR-IOV
- UMC 8.10 RAS fixes
- Don't restrict bpc to 8
- NBIO 7.5 fix
- Allow freesync on PCon for more devices
amdkfd:
- SDMA fix
- Illegal memory access fix
radeon:
- Display fix for iMac11,2
UAPI:
- Add some additional INFO IOCTL queries for GC 11 fixes
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230302051843.7793-1-alexander.deucher@amd.com
Diffstat (limited to 'include')
| -rw-r--r-- | include/uapi/drm/amdgpu_drm.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 973af6d06626..b6eb90df5d05 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -715,6 +715,7 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_IDS_FLAGS_FUSION 0x1 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 #define AMDGPU_IDS_FLAGS_TMZ 0x4 +#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 /* indicate if acceleration can be working */ #define AMDGPU_INFO_ACCEL_WORKING 0x00 @@ -1115,6 +1116,16 @@ struct drm_amdgpu_info_device { __u64 tcc_disabled_mask; __u64 min_engine_clock; __u64 min_memory_clock; + /* The following fields are only set on gfx11+, older chips set 0. */ + __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ + __u32 num_sqc_per_wgp; + __u32 sqc_data_cache_size; /* AKA SMEM cache */ + __u32 sqc_inst_cache_size; + __u32 gl1c_cache_size; + __u32 gl2c_cache_size; + __u64 mall_size; /* AKA infinity cache */ + /* high 32 bits of the rb pipes mask */ + __u32 enabled_rb_pipes_mask_hi; }; struct drm_amdgpu_info_hw_ip { |