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| author | Stephen Boyd <sboyd@kernel.org> | 2024-04-19 14:16:52 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-04-19 14:16:52 -0700 |
| commit | a09b2d6a3be5e7856e1a664bcfaaa3dcd6583b91 (patch) | |
| tree | e74973afcea064a6ed1705dbea500b4985995a85 /include | |
| parent | 4cece764965020c22cff7665b18a012006359095 (diff) | |
| parent | c0516eb4cf04ac61b6fe1f86cc15b2f5f024ee78 (diff) | |
| download | linux-a09b2d6a3be5e7856e1a664bcfaaa3dcd6583b91.tar.gz linux-a09b2d6a3be5e7856e1a664bcfaaa3dcd6583b91.tar.bz2 linux-a09b2d6a3be5e7856e1a664bcfaaa3dcd6583b91.zip | |
Merge tag 'renesas-clk-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on R-Car V4M
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779h0: Add timer clocks
clk: renesas: r8a779h0: Add SCIF clocks
clk: renesas: r9a07g044: Mark resets array as const
clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
clk: renesas: r8a779h0: Add thermal clock
dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/r9a07g043-cpg.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h index 77cde8effdc7..a64139fec815 100644 --- a/include/dt-bindings/clock/r9a07g043-cpg.h +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -16,15 +16,15 @@ #define R9A07G043_CLK_SD0 5 #define R9A07G043_CLK_SD1 6 #define R9A07G043_CLK_M0 7 -#define R9A07G043_CLK_M2 8 -#define R9A07G043_CLK_M3 9 +#define R9A07G043_CLK_M2 8 /* RZ/G2UL Only */ +#define R9A07G043_CLK_M3 9 /* RZ/G2UL Only */ #define R9A07G043_CLK_HP 10 #define R9A07G043_CLK_TSU 11 #define R9A07G043_CLK_ZT 12 #define R9A07G043_CLK_P0 13 #define R9A07G043_CLK_P1 14 #define R9A07G043_CLK_P2 15 -#define R9A07G043_CLK_AT 16 +#define R9A07G043_CLK_AT 16 /* RZ/G2UL Only */ #define R9A07G043_OSCCLK 17 #define R9A07G043_CLK_P0_DIV2 18 |