diff options
| author | Leo Li <sunpeng.li@amd.com> | 2024-12-11 12:06:24 -0500 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-01-23 17:23:01 +0100 |
| commit | 4e4ab0748cd8c3ffb81a3fec735bce5a3dc3ec01 (patch) | |
| tree | 7864435846504c23e526ff81c7a436393f559819 /mm/huge_memory.c | |
| parent | 6f8a91d9aeb505d3e9f67f9c5cdaffb86ddb6b4a (diff) | |
| download | linux-4e4ab0748cd8c3ffb81a3fec735bce5a3dc3ec01.tar.gz linux-4e4ab0748cd8c3ffb81a3fec735bce5a3dc3ec01.tar.bz2 linux-4e4ab0748cd8c3ffb81a3fec735bce5a3dc3ec01.zip | |
drm/amd/display: Do not elevate mem_type change to full update
commit 35ca53b7b0f0ffd16c6675fd76abac9409cf83e0 upstream.
[Why]
There should not be any need to revalidate bandwidth on memory placement
change, since the fb is expected to be pinned to DCN-accessable memory
before scanout. For APU it's DRAM, and DGPU, it's VRAM. However, async
flips + memory type change needs to be rejected.
[How]
Do not set lock_and_validation_needed on mem_type change. Instead,
reject an async_flip request if the crtc's buffer(s) changed mem_type.
This may fix stuttering/corruption experienced with PSR SU and PSR1
panels, if the compositor allocates fbs in both VRAM carveout and GTT
and flips between them.
Fixes: a7c0cad0dc06 ("drm/amd/display: ensure async flips are only accepted for fast updates")
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 4caacd1671b7a013ad04cd8b6398f002540bdd4d)
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'mm/huge_memory.c')
0 files changed, 0 insertions, 0 deletions
