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| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2024-12-16 23:45:54 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-01-09 13:33:39 +0100 |
| commit | 6bf65f39701e39239461bf5035b71a1b49ba78e6 (patch) | |
| tree | 67eef31a9999c3d5826cbf5ffbf1bb1b4830390f /scripts/objdiff | |
| parent | 9f6f54e6a6863131442b40e14d1792b090c7ce21 (diff) | |
| download | linux-6bf65f39701e39239461bf5035b71a1b49ba78e6.tar.gz linux-6bf65f39701e39239461bf5035b71a1b49ba78e6.tar.bz2 linux-6bf65f39701e39239461bf5035b71a1b49ba78e6.zip | |
drm/i915/cx0_phy: Fix C10 pll programming sequence
[ Upstream commit 385a95cc72941c7f88630a7bc4176048cc03b395 ]
According to spec VDR_CUSTOM_WIDTH register gets programmed after pll
specific VDR registers and TX Lane programming registers are done.
Moreover we only program into C10_VDR_CONTROL1 to update config and
setup master lane once all VDR registers are written into.
Bspec: 67636
Fixes: 51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241216181554.2861381-1-suraj.kandpal@intel.com
(cherry picked from commit f9d418552ba1e3a0e92487ff82eb515dab7516c0)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'scripts/objdiff')
0 files changed, 0 insertions, 0 deletions