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| author | Huacai Chen <chenhuacai@loongson.cn> | 2024-06-22 12:33:38 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-07-05 09:34:01 +0200 |
| commit | d2683b2d1ec266b39cf969df2dde17a464e1db3e (patch) | |
| tree | 1624c25b9118e360123d62dac4d16d9415485e67 /scripts | |
| parent | 52bbae429b86d9d335ba5c6819e9bdf906a47590 (diff) | |
| download | linux-d2683b2d1ec266b39cf969df2dde17a464e1db3e.tar.gz linux-d2683b2d1ec266b39cf969df2dde17a464e1db3e.tar.bz2 linux-d2683b2d1ec266b39cf969df2dde17a464e1db3e.zip | |
irqchip/loongson-liointc: Set different ISRs for different cores
commit a9c3ee5d0fdb069b54902300df6ac822027f3b0a upstream.
The liointc hardware provides separate Interrupt Status Registers (ISR) for
each core. The current code uses always the ISR of core #0, which works
during boot because by default all interrupts are routed to core #0.
When the interrupt routing changes in the firmware configuration then this
causes interrupts to be lost because they are not configured in the
corresponding core.
Use the core index to access the correct ISR instead of a hardcoded 0.
[ tglx: Massaged changelog ]
Fixes: 0858ed035a85 ("irqchip/loongson-liointc: Add ACPI init support")
Co-developed-by: Tianli Xiong <xiongtianli@loongson.cn>
Signed-off-by: Tianli Xiong <xiongtianli@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20240622043338.1566945-1-chenhuacai@loongson.cn
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions