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| author | Tony Lindgren <tony@atomide.com> | 2019-09-23 10:32:38 -0700 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2019-09-23 10:33:12 -0700 |
| commit | 2d3c8ba3cffa00f76bedb713c8c2126c82d8cd13 (patch) | |
| tree | b0323d24eba486b9dd17a8d6fbb2b7a41c76e3a1 /tools/perf/scripts/python/bin | |
| parent | dd8882a255388ba66175098b1560d4f81c100d30 (diff) | |
| download | linux-2d3c8ba3cffa00f76bedb713c8c2126c82d8cd13.tar.gz linux-2d3c8ba3cffa00f76bedb713c8c2126c82d8cd13.tar.bz2 linux-2d3c8ba3cffa00f76bedb713c8c2126c82d8cd13.zip | |
ARM: dts: Fix wrong clocks for dra7 mcasp
The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
This causes the following warning on beagle-x15:
ti-sysc 48468000.target-module: could not add child clock ahclkr: -19
Also the mcasp clkctrl clock bits are wrong:
For mcasp1 and 2 we have four clocks at bits 28, 24, 22 and 0:
bit 28 is ahclkr
bit 24 is ahclkx
bit 22 is auxclk
bit 0 is fck
For mcasp3 to 8 we have three clocks at bits 24, 22 and 0.
bit 24 is ahclkx
bit 22 is auxclk
bit 0 is fck
We do not have currently mapped auxclk at bit 22 for the drivers, that can
be added if needed.
Fixes: 5241ccbf2819 ("ARM: dts: Add missing ranges for dra7 mcasp l3 ports")
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions