MIPS: fix case mismatch in local_r4k_flush_icache_range()

Currently, Loongson-2 call protected_blast_icache_range() and others
call protected_loongson23_blast_icache_range(), but I think the correct
behavior should be the opposite.  BTW, Loongson-3's cache-ops is
compatible with MIPS64, but not compatible with Loongson-2.  So, rename
xxx_loongson23_yyy things to xxx_loongson2_yyy.

The patch fixes early boot hang with 3.13-rc1, introduced in commit
14bd8c082016 ("MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over
arch/mips").

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index c75025f27c201f02a9b85f65c2fdbbc529768325..06b9bc7ea14b1da802dc29090174230cc2e1d613 100644 (file)
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -83,6 +83,6 @@
 /*
  * Loongson2-specific cacheops
  */
 /*
  * Loongson2-specific cacheops
  */

-#define Hit_Invalidate_I_Loongson23    0x00
+#define Hit_Invalidate_I_Loongson2     0x00

 
 #endif /* __ASM_CACHEOPS_H */
 
 #endif /* __ASM_CACHEOPS_H */

diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 34d1a19171257ff8d8e602988615b8b8e2878ff9..91d20b08246f27304cdf17c28057428bd73af6de 100644 (file)
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -165,7 +165,7 @@ static inline void flush_icache_line(unsigned long addr)
        __iflush_prologue
        switch (boot_cpu_type()) {
        case CPU_LOONGSON2:
        __iflush_prologue
        switch (boot_cpu_type()) {
        case CPU_LOONGSON2:

-               cache_op(Hit_Invalidate_I_Loongson23, addr);
+               cache_op(Hit_Invalidate_I_Loongson2, addr);

                break;
 
        default:
                break;
 
        default:


@@ -219,7 +219,7 @@ static inline void protected_flush_icache_line(unsigned long addr)
 {
        switch (boot_cpu_type()) {
        case CPU_LOONGSON2:
 {
        switch (boot_cpu_type()) {
        case CPU_LOONGSON2:

-               protected_cache_op(Hit_Invalidate_I_Loongson23, addr);
+               protected_cache_op(Hit_Invalidate_I_Loongson2, addr);

                break;
 
        default:
                break;
 
        default:


@@ -452,8 +452,8 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )

-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \
-       protected_, loongson23_)
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
+       protected_, loongson2_)

 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
 /* blast_inv_dcache_range */
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
 /* blast_inv_dcache_range */

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 62ffd20ea86909be81906691dd1531a35733c410..73f02da61bafa12ecb4077da2f2f429eaba422c7 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -580,11 +580,11 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo
        else {
                switch (boot_cpu_type()) {
                case CPU_LOONGSON2:
        else {
                switch (boot_cpu_type()) {
                case CPU_LOONGSON2:

-                       protected_blast_icache_range(start, end);
+                       protected_loongson2_blast_icache_range(start, end);

                        break;
 
                default:
                        break;
 
                default:

-                       protected_loongson23_blast_icache_range(start, end);
+                       protected_blast_icache_range(start, end);

                        break;
                }
        }
                        break;
                }
        }