- div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
- mclk_req_rate = bclk_rate * div_bclk;
-
- if (mclk_rate < mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX ||
- mclk_rate > mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) {
- dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n",
- mclk_rate, mclk_req_rate, CLK_SHIFT_RATE_HZ_MAX);
- ret = -EINVAL;
- goto err_xfer_unlock;
+ if (ret == 0) {
+ regmap_update_bits(sai->regmap, SAI_FSCR,
+ SAI_FSCR_FW_MASK | SAI_FSCR_FPW_MASK, fscr);
+
+ if (sai->is_master_mode) {
+ bclk_rate = sai->fw_ratio * slot_width *
+ ch_per_lane * params_rate(params);
+ ret = clk_set_rate(sai->mclk, sai->mclk_rate);
+ if (ret)
+ dev_err(sai->dev, "Failed to set mclk to %u: %pe\n",
+ sai->mclk_rate, ERR_PTR(ret));
+ else {
+ mclk_rate = clk_get_rate(sai->mclk);
+ if (mclk_rate < bclk_rate) {
+ dev_err(sai->dev, "Mismatch mclk: %u, at least %u\n",
+ mclk_rate, bclk_rate);
+ ret = -EINVAL;
+ } else {
+
+ div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
+ mclk_req_rate = bclk_rate * div_bclk;
+
+ if (mclk_rate <
+ mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX ||
+ mclk_rate >
+ mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) {
+ dev_err(sai->dev,
+ "Mismatch mclk: %u, expected %u (+/- %dHz)\n",
+ mclk_rate, mclk_req_rate,
+ CLK_SHIFT_RATE_HZ_MAX);
+ ret = -EINVAL;
+ } else
+ regmap_update_bits(sai->regmap,
+ SAI_CKR,
+ SAI_CKR_MDIV_MASK,
+ SAI_CKR_MDIV(div_bclk));
+ }
+ }
+ }