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-rw-r--r--Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml68
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml82
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml60
-rw-r--r--MAINTAINERS6
-rw-r--r--arch/mips/ralink/mt7621.c6
-rw-r--r--drivers/clk/Kconfig1
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/at91/sama7g5.c6
-rw-r--r--drivers/clk/clk.c20
-rw-r--r--drivers/clk/imx/clk-imx25.c12
-rw-r--r--drivers/clk/imx/clk-imx27.c13
-rw-r--r--drivers/clk/imx/clk-imx35.c10
-rw-r--r--drivers/clk/imx/clk-imx5.c30
-rw-r--r--drivers/clk/imx/clk-imx6q.c16
-rw-r--r--drivers/clk/imx/clk-imx6sl.c16
-rw-r--r--drivers/clk/imx/clk-imx6sll.c24
-rw-r--r--drivers/clk/imx/clk-imx6sx.c16
-rw-r--r--drivers/clk/imx/clk-imx7d.c22
-rw-r--r--drivers/clk/imx/clk-imx7ulp.c31
-rw-r--r--drivers/clk/imx/clk-imx8mm.c18
-rw-r--r--drivers/clk/imx/clk-imx8mn.c18
-rw-r--r--drivers/clk/imx/clk-imx8mp.c32
-rw-r--r--drivers/clk/imx/clk-imx8mq.c22
-rw-r--r--drivers/clk/imx/clk-lpcg-scu.c1
-rw-r--r--drivers/clk/imx/clk-scu.c1
-rw-r--r--drivers/clk/imx/clk.c41
-rw-r--r--drivers/clk/imx/clk.h4
-rw-r--r--drivers/clk/qcom/a53-pll.c1
-rw-r--r--drivers/clk/qcom/a7-pll.c1
-rw-r--r--drivers/clk/qcom/apss-ipq-pll.c1
-rw-r--r--drivers/clk/qcom/clk-rpmh.c2
-rw-r--r--drivers/clk/qcom/dispcc-sc7180.c70
-rw-r--r--drivers/clk/qcom/dispcc-sdm845.c217
-rw-r--r--drivers/clk/qcom/dispcc-sm8250.c124
-rw-r--r--drivers/clk/qcom/gcc-sc7180.c196
-rw-r--r--drivers/clk/qcom/gcc-sc7280.c248
-rw-r--r--drivers/clk/qcom/gcc-sc8180x.c122
-rw-r--r--drivers/clk/qcom/gcc-sdm845.c650
-rw-r--r--drivers/clk/qcom/gcc-sdx55.c8
-rw-r--r--drivers/clk/qcom/gcc-sm8150.c100
-rw-r--r--drivers/clk/qcom/gcc-sm8250.c345
-rw-r--r--drivers/clk/qcom/gcc-sm8350.c418
-rw-r--r--drivers/clk/qcom/gpucc-sc7180.c3
-rw-r--r--drivers/clk/qcom/gpucc-sdm845.c45
-rw-r--r--drivers/clk/qcom/gpucc-sm8150.c9
-rw-r--r--drivers/clk/qcom/gpucc-sm8250.c9
-rw-r--r--drivers/clk/qcom/videocc-sc7180.c4
-rw-r--r--drivers/clk/qcom/videocc-sdm845.c55
-rw-r--r--drivers/clk/qcom/videocc-sm8150.c20
-rw-r--r--drivers/clk/qcom/videocc-sm8250.c30
-rw-r--r--drivers/clk/ralink/Kconfig11
-rw-r--r--drivers/clk/ralink/Makefile2
-rw-r--r--drivers/clk/ralink/clk-mt7621.c495
-rw-r--r--drivers/clk/renesas/clk-div6.c3
-rw-r--r--drivers/clk/renesas/clk-mstp.c2
-rw-r--r--drivers/clk/renesas/r8a7795-cpg-mssr.c6
-rw-r--r--drivers/clk/renesas/r8a77965-cpg-mssr.c1
-rw-r--r--drivers/clk/renesas/r8a77990-cpg-mssr.c1
-rw-r--r--drivers/clk/renesas/r8a779a0-cpg-mssr.c11
-rw-r--r--drivers/clk/renesas/r9a06g032-clocks.c12
-rw-r--r--drivers/clk/renesas/rcar-cpg-lib.c2
-rw-r--r--drivers/clk/renesas/rcar-gen2-cpg.c3
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.c2
-rw-r--r--drivers/clk/renesas/rcar-usb2-clock-sel.c5
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c2
-rw-r--r--drivers/clk/rockchip/Kconfig29
-rw-r--r--drivers/clk/rockchip/Makefile1
-rw-r--r--drivers/clk/rockchip/clk-cpu.c53
-rw-r--r--drivers/clk/rockchip/clk-px30.c7
-rw-r--r--drivers/clk/rockchip/clk-rk3036.c7
-rw-r--r--drivers/clk/rockchip/clk-rk3128.c7
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c14
-rw-r--r--drivers/clk/rockchip/clk-rk3228.c7
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c7
-rw-r--r--drivers/clk/rockchip/clk-rk3308.c7
-rw-r--r--drivers/clk/rockchip/clk-rk3328.c7
-rw-r--r--drivers/clk/rockchip/clk-rk3368.c14
-rw-r--r--drivers/clk/rockchip/clk-rk3399.c15
-rw-r--r--drivers/clk/rockchip/clk-rk3568.c1725
-rw-r--r--drivers/clk/rockchip/clk-rv1108.c7
-rw-r--r--drivers/clk/rockchip/clk.h54
-rw-r--r--drivers/clk/samsung/clk-exynos4412-isp.c4
-rw-r--r--drivers/clk/samsung/clk-exynos7.c7
-rw-r--r--drivers/clk/samsung/clk-s5pv210-audss.c4
-rw-r--r--drivers/clk/socfpga/clk-agilex.c117
-rw-r--r--drivers/clk/socfpga/clk-gate-a10.c9
-rw-r--r--drivers/clk/socfpga/clk-gate-s10.c17
-rw-r--r--drivers/clk/socfpga/clk-gate.c11
-rw-r--r--drivers/clk/socfpga/clk-periph-a10.c11
-rw-r--r--drivers/clk/socfpga/clk-periph-s10.c42
-rw-r--r--drivers/clk/socfpga/clk-periph.c8
-rw-r--r--drivers/clk/socfpga/clk-pll-a10.c12
-rw-r--r--drivers/clk/socfpga/clk-pll-s10.c45
-rw-r--r--drivers/clk/socfpga/clk-pll.c18
-rw-r--r--drivers/clk/socfpga/clk-s10.c68
-rw-r--r--drivers/clk/socfpga/stratix10-clk.h24
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-v3s.c33
-rw-r--r--drivers/clk/sunxi/clk-sun6i-ar100.c2
-rw-r--r--drivers/clk/sunxi/clk-sun9i-core.c8
-rw-r--r--drivers/clk/sunxi/clk-usb.c2
-rw-r--r--drivers/clk/uniphier/clk-uniphier-mux.c4
-rw-r--r--drivers/clk/zynqmp/Kconfig4
-rw-r--r--drivers/clk/zynqmp/pll.c24
-rw-r--r--drivers/staging/mt7621-dts/gbpc1.dts11
-rw-r--r--drivers/staging/mt7621-dts/mt7621.dtsi82
-rw-r--r--include/dt-bindings/clock/imx8mp-clock.h3
-rw-r--r--include/dt-bindings/clock/mt7621-clk.h41
-rw-r--r--include/dt-bindings/clock/rk3568-cru.h926
109 files changed, 5279 insertions, 2034 deletions
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
new file mode 100644
index 000000000000..915f84efd763
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
+
+description: |
+ The MT7621 has a PLL controller from where the cpu clock is provided
+ as well as derived clocks for the bus and the peripherals. It also
+ can gate SoC device clocks.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify the clock which they consume.
+
+ All these identifiers could be found in:
+ [1]: <include/dt-bindings/clock/mt7621-clk.h>.
+
+ The clocks are provided inside a system controller node.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt7621-sysc
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ description:
+ The first cell indicates the clock number, see [1] for available
+ clocks.
+ const: 1
+
+ ralink,memctl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle of syscon used to control memory registers
+
+ clock-output-names:
+ maxItems: 8
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - ralink,memctl
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt7621-clk.h>
+
+ sysc: sysc@0 {
+ compatible = "mediatek,mt7621-sysc", "syscon";
+ reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ ralink,memctl = <&memc>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
+ "250m", "270m";
+ };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
new file mode 100644
index 000000000000..d902f137ab17
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on SDM845
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-sdm845.h
+
+properties:
+ compatible:
+ const: qcom,gcc-sdm845
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board active XO source
+ - description: Sleep clock source
+ - description: PCIE 0 Pipe clock source
+ - description: PCIE 1 Pipe clock source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: bi_tcxo_ao
+ - const: sleep_clk
+ - const: pcie_0_pipe_clk
+ - const: pcie_1_pipe_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ protected-clocks:
+ description:
+ Protected clock specifier list as per common clock binding.
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ # Example for GCC for SDM845:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,gcc-sdm845";
+ reg = <0x100000 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie0_lane>,
+ <&pcie1_lane>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index ee0467fb5e31..490edad25830 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -32,7 +32,6 @@ description: |
- dt-bindings/clock/qcom,gcc-mdm9615.h
- dt-bindings/reset/qcom,gcc-mdm9615.h
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
- - dt-bindings/clock/qcom,gcc-sdm845.h
properties:
compatible:
@@ -52,7 +51,6 @@ properties:
- qcom,gcc-mdm9615
- qcom,gcc-sdm630
- qcom,gcc-sdm660
- - qcom,gcc-sdm845
'#clock-cells':
const: 1
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
new file mode 100644
index 000000000000..b2c26097827f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROCKCHIP rk3568 Family Clock Control Module Binding
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3568 clock controller generates the clock and also implements a
+ reset controller for SoC peripherals.
+ (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
+ used in device tree sources.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-cru
+ - rockchip,rk3568-pmucru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+ pmucru: clock-controller@fdd00000 {
+ compatible = "rockchip,rk3568-pmucru";
+ reg = <0xfdd00000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ - |
+ cru: clock-controller@fdd20000 {
+ compatible = "rockchip,rk3568-cru";
+ reg = <0xfdd20000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 8f4a072f47ae..5c90148f0369 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11469,6 +11469,12 @@ L: linux-wirele