diff options
81 files changed, 2549 insertions, 1981 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 3d041d0d16e8..d3f3a60fbf25 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -284,7 +284,7 @@ following manner: processors") to bring CPUs into the kernel. The device tree should contain a 'psci' node, as described in - Documentation/devicetree/bindings/arm/psci.txt. + Documentation/devicetree/bindings/arm/psci.yaml. - Secondary CPU general-purpose register settings x0 = 0 (reserved for future use) diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile index 8a2774b5834b..6b0dfd5c17ba 100644 --- a/Documentation/devicetree/bindings/Makefile +++ b/Documentation/devicetree/bindings/Makefile @@ -25,7 +25,7 @@ DT_DOCS = $(shell \ DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS)) extra-y += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES)) -extra-y += $(patsubst $(src)/%.yaml,%.example.dtb, $(DT_SCHEMA_FILES)) +extra-y += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES)) $(obj)/$(DT_TMP_SCHEMA): $(DT_SCHEMA_FILES) FORCE $(call if_changed,mk_schema) diff --git a/Documentation/devicetree/bindings/arm/al,alpine.txt b/Documentation/devicetree/bindings/arm/al,alpine.txt deleted file mode 100644 index d00debe2e86f..000000000000 --- a/Documentation/devicetree/bindings/arm/al,alpine.txt +++ /dev/null @@ -1,16 +0,0 @@ -Annapurna Labs Alpine Platform Device Tree Bindings ---------------------------------------------------------------- - -Boards in the Alpine family shall have the following properties: - -* Required root node properties: -compatible: must contain "al,alpine" - -* Example: - -/ { - model = "Annapurna Labs Alpine Dev Board"; - compatible = "al,alpine"; - - ... -} diff --git a/Documentation/devicetree/bindings/arm/al,alpine.yaml b/Documentation/devicetree/bindings/arm/al,alpine.yaml new file mode 100644 index 000000000000..a70dff277e05 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/al,alpine.yaml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/al,alpine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Annapurna Labs Alpine Platform Device Tree Bindings + +maintainers: + - Tsahee Zidenberg <tsahee@annapurnalabs.com> + - Antoine Tenart <antoine.tenart@bootlin.com> + +properties: + compatible: + items: + - const: al,alpine + model: + items: + - const: "Annapurna Labs Alpine Dev Board" + +... diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index abff8d834a6a..6758ece324b1 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards @@ -197,7 +197,7 @@ Required nodes: The description for the board must include: - a "psci" node describing the boot method used for the secondary CPUs. A detailed description of the bindings used for "psci" nodes is present - in the psci.txt file. + in the psci.yaml file. - a "cpus" node describing the available cores and their associated "enable-method"s. For more details see cpus.txt file. diff --git a/Documentation/devicetree/bindings/arm/axxia.txt b/Documentation/devicetree/bindings/arm/axxia.txt deleted file mode 100644 index 7b4ef9c07696..000000000000 --- a/Documentation/devicetree/bindings/arm/axxia.txt +++ /dev/null @@ -1,12 +0,0 @@ -Axxia AXM55xx device tree bindings - -Boards using the AXM55xx SoC need to have the following properties: - -Required root node property: - - - compatible = "lsi,axm5516" - -Boards: - - LSI AXM5516 Validation board (Amarillo) - compatible = "lsi,axm5516-amarillo", "lsi,axm5516" diff --git a/Documentation/devicetree/bindings/arm/axxia.yaml b/Documentation/devicetree/bindings/arm/axxia.yaml new file mode 100644 index 000000000000..98780a569f22 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/axxia.yaml @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/axxia.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axxia AXM55xx device tree bindings + +maintainers: + - Anders Berg <anders.berg@lsi.com> + +properties: + compatible: + description: LSI AXM5516 Validation board (Amarillo) + items: + - const: lsi,axm5516-amarillo + - const: lsi,axm5516 + +... diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 591bbd012d63..aa40b074b864 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -39,281 +39,242 @@ description: |+ described below. properties: - $nodename: - const: cpus - description: Container of cpu nodes - - '#address-cells': - enum: [1, 2] + reg: + maxItems: 1 description: | - Definition depends on ARM architecture version and configuration: + Usage and definition depend on ARM architecture version and + configuration: On uniprocessor ARM architectures previous to v7 - value must be 1, to enable a simple enumeration - scheme for processors that do not have a HW CPU - identification register. - On 32-bit ARM 11 MPcore, ARM v7 or later systems - value must be 1, that corresponds to CPUID/MPIDR - registers sizes. - On ARM v8 64-bit systems value should be set to 2, - that corresponds to the MPIDR_EL1 register size. - If MPIDR_EL1[63:32] value is equal to 0 on all CPUs - in the system, #address-cells can be set to 1, since - MPIDR_EL1[63:32] bits are not used for CPUs - identification. - - '#size-cells': - const: 0 - -patternProperties: - '^cpu@[0-9a-f]+$': - type: object - properties: - device_type: - const: cpu - - reg: - maxItems: 1 - description: | - Usage and definition depend on ARM architecture version and - configuration: - - On uniprocessor ARM architectures previous to v7 - this property is required and must be set to 0. - - On ARM 11 MPcore based systems this property is - required and matches the CPUID[11:0] register bits. - - Bits [11:0] in the reg cell must be set to - bits [11:0] in CPU ID register. - - All other bits in the reg cell must be set to 0. - - On 32-bit ARM v7 or later systems this property is - required and matches the CPU MPIDR[23:0] register - bits. - - Bits [23:0] in the reg cell must be set to - bits [23:0] in MPIDR. - - All other bits in the reg cell must be set to 0. - - On ARM v8 64-bit systems this property is required - and matches the MPIDR_EL1 register affinity bits. + this property is required and must be set to 0. + + On ARM 11 MPcore based systems this property is + required and matches the CPUID[11:0] register bits. + + Bits [11:0] in the reg cell must be set to + bits [11:0] in CPU ID register. + + All other bits in the reg cell must be set to 0. + + On 32-bit ARM v7 or later systems this property is + required and matches the CPU MPIDR[23:0] register + bits. + + Bits [23:0] in the reg cell must be set to + bits [23:0] in MPIDR. + + All other bits in the reg cell must be set to 0. + + On ARM v8 64-bit systems this property is required + and matches the MPIDR_EL1 register affinity bits. + + * If cpus node's #address-cells property is set to 2 + + The first reg cell bits [7:0] must be set to + bits [39:32] of MPIDR_EL1. + + The second reg cell bits [23:0] must be set to + bits [23:0] of MPIDR_EL1. + + * If cpus node's #address-cells property is set to 1 + + The reg cell bits [23:0] must be set to bits [23:0] + of MPIDR_EL1. + + All other bits in the reg cells must be set to 0. + + compatible: + enum: + - arm,arm710t + - arm,arm720t + - arm,arm740t + - arm,arm7ej-s + - arm,arm7tdmi + - arm,arm7tdmi-s + - arm,arm9es + - arm,arm9ej-s + - arm,arm920t + - arm,arm922t + - arm,arm925 + - arm,arm926e-s + - arm,arm926ej-s + - arm,arm940t + - arm,arm946e-s + - arm,arm966e-s + - arm,arm968e-s + - arm,arm9tdmi + - arm,arm1020e + - arm,arm1020t + - arm,arm1022e + - arm,arm1026ej-s + - arm,arm1136j-s + - arm,arm1136jf-s + - arm,arm1156t2-s + - arm,arm1156t2f-s + - arm,arm1176jzf + - arm,arm1176jz-s + - arm,arm1176jzf-s + - arm,arm11mpcore + - arm,armv8 # Only for s/w models + - arm,cortex-a5 + - arm,cortex-a7 + - arm,cortex-a8 + - arm,cortex-a9 + - arm,cortex-a12 + - arm,cortex-a15 + - arm,cortex-a17 + - arm,cortex-a53 + - arm,cortex-a57 + - arm,cortex-a72 + - arm,cortex-a73 + - arm,cortex-m0 + - arm,cortex-m0+ + - arm,cortex-m1 + - arm,cortex-m3 + - arm,cortex-m4 + - arm,cortex-r4 + - arm,cortex-r5 + - arm,cortex-r7 + - brcm,brahma-b15 + - brcm,brahma-b53 + - brcm,vulcan + - cavium,thunder + - cavium,thunder2 + - faraday,fa526 + - intel,sa110 + - intel,sa1100 + - marvell,feroceon + - marvell,mohawk + - marvell,pj4a + - marvell,pj4b + - marvell,sheeva-v5 + - marvell,sheeva-v7 + - nvidia,tegra132-denver + - nvidia,tegra186-denver + - nvidia,tegra194-carmel + - qcom,krait + - qcom,kryo + - qcom,kryo385 + - qcom,scorpion + + enable-method: + allOf: + - $ref: '/schemas/types.yaml#/definitions/string' + - oneOf: + # On ARM v8 64-bit this property is required + - enum: + - psci + - spin-table + # On ARM 32-bit systems this property is optional + - enum: + - actions,s500-smp + - allwinner,sun6i-a31 + - allwinner,sun8i-a23 + - allwinner,sun9i-a80-smp + - allwinner,sun8i-a83t-smp + - amlogic,meson8-smp + - amlogic,meson8b-smp + - arm,realview-smp + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm2836-smp + - brcm,bcm63138 + - brcm,bcm-nsp-smp + - brcm,brahma-b15 + - marvell,armada-375-smp + - marvell,armada-380-smp + - marvell,armada-390-smp + - marvell,armada-xp-smp + - marvell,98dx3236-smp + - mediatek,mt6589-smp + - mediatek,mt81xx-tz-smp + - qcom,gcc-msm8660 + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + - renesas,apmu + - renesas,r9a06g032-smp + - rockchip,rk3036-smp + - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp + - ste,dbx500-smp + + cpu-release-addr: + $ref: '/schemas/types.yaml#/definitions/uint64' + + description: + Required for systems that have an "enable-method" + property value of "spin-table". + On ARM v8 64-bit systems must be a two cell + property identifying a 64-bit zero-initialised + memory location. + + cpu-idle-states: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: | + List of phandles to idle state nodes supported + by this cpu (see ./idle-states.txt). + + capacity-dmips-mhz: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + u32 value representing CPU capacity (see ./cpu-capacity.txt) in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + + dynamic-power-coefficient: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + A u32 value that represents the running time dynamic + power coefficient in units of uW/MHz/V^2. The + coefficient can either be calculated from power + measurements or derived by analysis. + + The dynamic power consumption of the CPU is + proportional to the square of the Voltage (V) and + the clock frequency (f). The coefficient is used to + calculate the dynamic power as below - + + Pdyn = dynamic-power-coefficient * V^2 * f + + where voltage is in V, frequency is in MHz. + + qcom,saw: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the SAW* node associated with this CPU. - * If cpus node's #address-cells property is set to 2 + Required for systems that have an "enable-method" property + value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" - The first reg cell bits [7:0] must be set to - bits [39:32] of MPIDR_EL1. + * arm/msm/qcom,saw2.txt - The second reg cell bits [23:0] must be set to - bits [23:0] of MPIDR_EL1. + qcom,acc: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the ACC* node associated with this CPU. - * If cpus node's #address-cells property is set to 1 + Required for systems that have an "enable-meth |