diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/hwss')
5 files changed, 50 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 6d40e93b5497..6d9ec802f1bb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -519,6 +519,17 @@ void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_ } } +void dcn35_symclk_root_clock_control(struct dce_hwseq *hws, unsigned int enc_inst, bool clock_on) +{ + if (!hws->ctx->dc->debug.root_clock_optimization.bits.symclk_fe) + return; + + if (hws->ctx->dc->res_pool->dccg->funcs->set_symclk_root_clock_gating) { + hws->ctx->dc->res_pool->dccg->funcs->set_symclk_root_clock_gating( + hws->ctx->dc->res_pool->dccg, enc_inst, enc_inst, clock_on); + } +} + void dcn35_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -1008,6 +1019,7 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, int i = 0, j = 0; int edp_num = 0; struct dc_link *edp_links[MAX_NUM_EDP] = { NULL }; + bool stream_enc_in_use[MAX_PIPES] = { false }; memset(update_state, 0, sizeof(struct pg_block_update)); @@ -1053,10 +1065,17 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, if (pipe_ctx->stream_res.hpo_dp_stream_enc) update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false; + + if (pipe_ctx->stream_res.stream_enc && + !pipe_ctx->stream_res.hpo_dp_stream_enc) + stream_enc_in_use[pipe_ctx->stream_res.stream_enc->stream_enc_inst] = true; } + for (i = 0; i < dc->res_pool->pipe_count; i++) + if (stream_enc_in_use[i]) + update_state->pg_pipe_res_update[PG_SYMCLK][i] = false; + for (i = 0; i < dc->link_count; i++) { - update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true; if (dc->links[i]->type != dc_connection_none) update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false; } @@ -1120,6 +1139,10 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, if (j == PG_DPSTREAM && new_pipe->stream_res.hpo_dp_stream_enc) update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true; + + if (j == PG_SYMCLK && new_pipe->stream_res.stream_enc && + !new_pipe->stream_res.hpo_dp_stream_enc) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.stream_enc->stream_enc_inst] = true; } } else if (cur_pipe->plane_state == new_pipe->plane_state || cur_pipe == new_pipe) { @@ -1154,6 +1177,12 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, cur_pipe->stream_res.hpo_dp_stream_enc != new_pipe->stream_res.hpo_dp_stream_enc && new_pipe->stream_res.hpo_dp_stream_enc) update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true; + + if (j == PG_SYMCLK && + new_pipe->stream_res.stream_enc && + cur_pipe->stream_res.stream_enc != new_pipe->stream_res.stream_enc && + !new_pipe->stream_res.hpo_dp_stream_enc) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.stream_enc->stream_enc_inst] = true; } } } @@ -1312,11 +1341,16 @@ void dcn35_root_clock_control(struct dc *dc, dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on); } - for (i = 0; i < dc->res_pool->dig_link_enc_count; i++) + for (i = 0; i < dc->res_pool->dig_link_enc_count; i++) { if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i]) if (dc->hwseq->funcs.physymclk_root_clock_control) dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on); + if (update_state->pg_pipe_res_update[PG_SYMCLK][i]) + if (dc->hwseq->funcs.symclk_root_clock_control) + dc->hwseq->funcs.symclk_root_clock_control(dc->hwseq, i, power_on); + } + } for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { if (update_state->pg_pipe_res_update[PG_DSC][i]) { @@ -1342,11 +1376,16 @@ void dcn35_root_clock_control(struct dc *dc, dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on); } - for (i = 0; i < dc->res_pool->dig_link_enc_count; i++) + for (i = 0; i < dc->res_pool->dig_link_enc_count; i++) { if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i]) if (dc->hwseq->funcs.physymclk_root_clock_control) dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on); + if (update_state->pg_pipe_res_update[PG_SYMCLK][i]) + if (dc->hwseq->funcs.symclk_root_clock_control) + dc->hwseq->funcs.symclk_root_clock_control(dc->hwseq, i, power_on); + } + } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h index bc05beba5f2c..503a8419bae7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h @@ -41,6 +41,8 @@ void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hp void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on); +void dcn35_symclk_root_clock_control(struct dce_hwseq *hws, unsigned int enc_inst, bool clock_on); + void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable); void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c index 663bacd1fafd..0b6d7d76c85b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c @@ -150,6 +150,7 @@ static const struct hwseq_private_funcs dcn35_private_funcs = { .dpp_root_clock_control = dcn35_dpp_root_clock_control, .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, + .symclk_root_clock_control = dcn35_symclk_root_clock_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn35_update_odm, .set_hdr_multiplier = dcn10_set_hdr_multiplier, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c index d8de1c6a84e8..e8643f305fd6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c @@ -149,6 +149,7 @@ static const struct hwseq_private_funcs dcn351_private_funcs = { .dpp_root_clock_control = dcn35_dpp_root_clock_control, .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, + .symclk_root_clock_control = dcn35_symclk_root_clock_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn35_update_odm, .set_hdr_multiplier = dcn10_set_hdr_multiplier, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h index 7ac3f2a09487..e2189795ca30 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h @@ -128,6 +128,10 @@ struct hwseq_private_funcs { struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on); + void (*symclk_root_clock_control)( + struct dce_hwseq *hws, + unsigned int enc_inst, + bool clock_on); void (*dpp_pg_control)(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on); |