diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/link')
10 files changed, 86 insertions, 80 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index fee71ebdfc73..a131e30fd7d6 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -60,6 +60,10 @@ */ #define LINK_TRAINING_MAX_VERIFY_RETRY 2 +static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u"; + +static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR"; + static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal) { enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE; @@ -494,8 +498,6 @@ static void query_hdcp_capability(enum signal_type signal, struct dc_link *link) dc_process_hdcp_msg(signal, link, &msg22); if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { - enum hdcp_message_status status = HDCP_MESSAGE_UNSUPPORTED; - msg14.data = &link->hdcp_caps.bcaps.raw; msg14.length = sizeof(link->hdcp_caps.bcaps.raw); msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS; @@ -503,7 +505,7 @@ static void query_hdcp_capability(enum signal_type signal, struct dc_link *link) msg14.link = HDCP_LINK_PRIMARY; msg14.max_retries = 5; - status = dc_process_hdcp_msg(signal, link, &msg14); + dc_process_hdcp_msg(signal, link, &msg14); } } @@ -830,7 +832,7 @@ static void verify_link_capability(struct dc_link *link, struct dc_sink *sink, verify_link_capability_non_destructive(link); } -/** +/* * detect_link_and_local_sink() - Detect if a sink is attached to a given link * * link->local_sink is created or destroyed as needed. @@ -1183,7 +1185,7 @@ static bool detect_link_and_local_sink(struct dc_link *link, return true; } -/** +/* * link_detect_connection_type() - Determine if there is a sink connected * * @type: Returned connection type @@ -1225,6 +1227,11 @@ bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type * /* TODO: need to do the actual detection */ } else { *type = dc_connection_none; + if (link->connector_signal == SIGNAL_TYPE_EDP) { + /* eDP is not connected, power down it */ + if (!link->dc->config.edp_no_power_sequencing) + link->dc->hwss.edp_power_control(link, false); + } } return true; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 020d668ce09e..f6c5ee2d639b 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -2160,6 +2160,7 @@ static enum dc_status enable_link_dp_mst( struct pipe_ctx *pipe_ctx) { struct dc_link *link = pipe_ctx->stream->link; + unsigned char mstm_cntl; /* sink signal type after MST branch is MST. Multiple MST sinks * share one link. Link DP PHY is enable or training only once. @@ -2168,7 +2169,9 @@ static enum dc_status enable_link_dp_mst( return DC_OK; /* clear payload table */ - dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); + core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); + if (mstm_cntl & DP_MST_EN) + dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); /* to make sure the pending down rep can be processed * before enabling the link @@ -2477,11 +2480,12 @@ void link_set_dpms_on( * from transmitter control. */ if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || - dp_is_128b_132b_signal(pipe_ctx))) - if (link_enc) - link_enc->funcs->setup( - link_enc, - pipe_ctx->stream->signal); + dp_is_128b_132b_signal(pipe_ctx))) { + if (link_enc) + link_enc->funcs->setup( + link_enc, + pipe_ctx->stream->signal); + } dc->hwss.enable_stream(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 3951d48118c4..1515c817f03b 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -99,6 +99,7 @@ static void construct_link_service_validation(struct link_service *link_srv) { link_srv->validate_mode_timing = link_validate_mode_timing; link_srv->dp_link_bandwidth_kbps = dp_link_bandwidth_kbps; + link_srv->validate_dpia_bandwidth = link_validate_dpia_bandwidth; } /* link dpms owns the programming sequence of stream's dpms state associated diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index 9a5010f86003..d4b7da526f0a 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -30,6 +30,7 @@ */ #include "link_validation.h" #include "protocols/link_dp_capability.h" +#include "protocols/link_dp_dpia_bw.h" #include "resource.h" #define DC_LOGGER_INIT(logger) @@ -255,57 +256,6 @@ uint32_t dp_link_bandwidth_kbps( return link_rate_per_lane_kbps * link_settings->lane_count / 10000 * total_data_bw_efficiency_x10000; } -uint32_t link_timing_bandwidth_kbps(const struct dc_crtc_timing *timing) -{ - uint32_t bits_per_channel = 0; - uint32_t kbps; - - if (timing->flags.DSC) - return dc_dsc_stream_bandwidth_in_kbps(timing, - timing->dsc_cfg.bits_per_pixel, - timing->dsc_cfg.num_slices_h, - timing->dsc_cfg.is_dp); - - switch (timing->display_color_depth) { - case COLOR_DEPTH_666: - bits_per_channel = 6; - break; - case COLOR_DEPTH_888: - bits_per_channel = 8; - break; - case COLOR_DEPTH_101010: - bits_per_channel = 10; - break; - case COLOR_DEPTH_121212: - bits_per_channel = 12; - break; - case COLOR_DEPTH_141414: - bits_per_channel = 14; - break; - case COLOR_DEPTH_161616: - bits_per_channel = 16; - break; - default: - ASSERT(bits_per_channel != 0); - bits_per_channel = 8; - break; - } - - kbps = timing->pix_clk_100hz / 10; - kbps *= bits_per_channel; - - if (timing->flags.Y_ONLY != 1) { - /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/ - kbps *= 3; - if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) - kbps /= 2; - else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) - kbps = kbps * 2 / 3; - } - - return kbps; -} - static bool dp_validate_mode_timing( struct dc_link *link, const struct dc_crtc_timing *timing) @@ -394,3 +344,20 @@ enum dc_status link_validate_mode_timing( return DC_OK; } + +bool link_validate_dpia_bandwidth(const struct dc_stream_state *stream, const unsigned int num_streams) +{ + bool ret = true; + int bw_needed[MAX_DPIA_NUM]; + struct dc_link *link[MAX_DPIA_NUM]; + + if (!num_streams || num_streams > MAX_DPIA_NUM) + return ret; + + for (uint8_t i = 0; i < num_streams; ++i) { + + link[i] = stream[i].link; + bw_needed[i] = dc_bandwidth_in_kbps_from_timing(&stream[i].timing); + } + return ret; +} diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.h b/drivers/gpu/drm/amd/display/dc/link/link_validation.h index 2191d3a4950c..4a954317d0da 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.h +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.h @@ -29,7 +29,11 @@ enum dc_status link_validate_mode_timing( const struct dc_stream_state *stream, struct dc_link *link, const struct dc_crtc_timing *timing); +bool link_validate_dpia_bandwidth( + const struct dc_stream_state *stream, + const unsigned int num_streams); uint32_t dp_link_bandwidth_kbps( const struct dc_link *link, const struct dc_link_settings *link_settings); + #endif /* __LINK_VALIDATION_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index e9bcb35ae185..c840ef17802e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -203,8 +203,11 @@ static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in case 5400000: link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane break; + case 6750000: + link_rate = LINK_RATE_RATE_8; // Rate_8 - 6.75 Gbps/Lane + break; case 8100000: - link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3)- 8.10 Gbps/Lane + link_rate = LINK_RATE_HIGH3; // Rate_9 (HBR3)- 8.10 Gbps/Lane break; default: link_rate = LINK_RATE_UNKNOWN; @@ -444,8 +447,12 @@ static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) } } -static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate) +static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate) { + // NEEDSWORK: provide some details about why this function never returns some of the + // obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such behavior is intended. + // + switch (link_rate) { case LINK_RATE_UHBR20: return LINK_RATE_UHBR13_5; @@ -454,13 +461,22 @@ static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate) case LINK_RATE_UHBR10: return LINK_RATE_HIGH3; case LINK_RATE_HIGH3: + if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5) + return LINK_RATE_RATE_8; + return LINK_RATE_HIGH2; + case LINK_RATE_RATE_8: return LINK_RATE_HIGH2; case LINK_RATE_HIGH2: return LINK_RATE_HIGH; + case LINK_RATE_RATE_6: + case LINK_RATE_RBR2: + return LINK_RATE_HIGH; case LINK_RATE_HIGH: return LINK_RATE_LOW; + case LINK_RATE_RATE_3: + case LINK_RATE_RATE_2: + return LINK_RATE_LOW; case LINK_RATE_LOW: - return LINK_RATE_UNKNOWN; default: return LINK_RATE_UNKNOWN; } @@ -583,7 +599,7 @@ bool decide_fallback_link_setting( case LINK_TRAINING_LQA_FAIL: { if (!reached_minimum_link_rate(cur->link_rate)) { - cur->link_rate = reduce_link_rate(cur->link_rate); + cur->link_rate = reduce_link_rate(link, cur->link_rate); } else if (!reached_minimum_lane_count(cur->lane_count)) { cur->link_rate = max->link_rate; if (training_result == LINK_TRAINING_CR_FAIL_LANE0) @@ -605,7 +621,7 @@ bool decide_fallback_link_setting( if (!reached_minimum_lane_count(cur->lane_count)) { cur->lane_count = reduce_lane_count(cur->lane_count); } else if (!reached_minimum_link_rate(cur->link_rate)) { - cur->link_rate = reduce_link_rate(cur->link_rate); + cur->link_rate = reduce_link_rate(link, cur->link_rate); /* Reduce max link rate to avoid potential infinite loop. * Needed so that any subsequent CR_FAIL fallback can't * re-set the link rate higher than the link rate from @@ -621,7 +637,7 @@ bool decide_fallback_link_setting( case LINK_TRAINING_EQ_FAIL_CR: { if (!reached_minimum_link_rate(cur->link_rate)) { - cur->link_rate = reduce_link_rate(cur->link_rate); + cur->link_rate = reduce_link_rate(link, cur->link_rate); /* Reduce max link rate to avoid potential infinite loop. * Needed so that any subsequent CR_FAIL fallback can't * re-set the link rate higher than the link rate from @@ -1284,7 +1300,7 @@ bool dp_overwrite_extended_receiver_cap(struct dc_link *link) void dpcd_set_source_specific_data(struct dc_link *link) { if (!link->dc->vendor_signature.is_valid) { - enum dc_status result_write_min_hblank = DC_NOT_SUPPORTED; + enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED; struct dpcd_amd_signature amd_signature = {0}; struct dpcd_amd_device_id amd_device_id = {0}; @@ -2177,7 +2193,7 @@ bool dp_verify_link_cap_with_retries( return success; } -/** +/* * Check if there is a native DP or passive DP-HDMI dongle connected */ bool dp_is_sink_present(struct dc_link *link) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c index 931f7c6446de..7581023daa47 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c @@ -33,10 +33,6 @@ #define DC_LOGGER \ link->ctx->logger -/* Number of Host Routers per motherboard is 2 */ -#define MAX_HR_NUM 2 -/* Number of DPIA per host router is 2 */ -#define MAX_DPIA_NUM (MAX_HR_NUM * 2) #define Kbps_TO_Gbps (1000 * 1000) // ------------------------------------------------------------------ @@ -379,9 +375,8 @@ void dpia_handle_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t res // 1. If due to unplug of other sink if (estimated == host_router_total_estimated_bw) { // First update the estimated & max_bw fields - if (link->dpia_bw_alloc_config.estimated_bw < estimated) { + if (link->dpia_bw_alloc_config.estimated_bw < estimated) link->dpia_bw_alloc_config.estimated_bw = estimated; - } } // 2. If due to realloc bw btw 2 dpia due to plug OR realloc unused Bw else { @@ -464,7 +459,7 @@ int link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int re out: return ret; } -bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed_per_dpia, uint8_t num_dpias) +bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed_per_dpia, const unsigned int num_dpias) { bool ret = true; int bw_needed_per_hr[MAX_HR_NUM] = { 0, 0 }; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h index 382616c8b698..7292690383ae 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h @@ -28,6 +28,11 @@ #include "link.h" +/* Number of Host Routers per motherboard is 2 */ +#define MAX_HR_NUM 2 +/* Number of DPIA per host router is 2 */ +#define MAX_DPIA_NUM (MAX_HR_NUM * 2) + /* * Host Router BW type */ @@ -92,6 +97,6 @@ void dpia_handle_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t res * * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE */ -bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed, uint8_t num_dpias); +bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed, const unsigned int num_dpias); #endif /* DC_INC_LINK_DP_DPIA_BW_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index a9025671ee4a..f301c9eaf2f9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -86,6 +86,9 @@ void dp_log_training_result( case LINK_RATE_HIGH2: link_rate = "HBR2"; break; + case LINK_RATE_RATE_8: + link_rate = "R8"; + break; case LINK_RATE_HIGH3: link_rate = "HBR3"; break; @@ -1580,8 +1583,7 @@ bool perform_link_training_with_retries( * Report and continue with eDP panel mode to * perform eDP link training with right settings */ - bool result; - result = cp_psp->funcs.enable_assr(cp_psp->handle, link); + cp_psp->funcs.enable_assr(cp_psp->handle, link); } } diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 93a6bbe954bb..d895046787bc 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -37,6 +37,11 @@ #include "abm.h" #define DC_LOGGER_INIT(logger) +/* Travis */ +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; +/* Nutmeg */ +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; + void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode) { union dpcd_edp_config edp_config_set; |