diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include')
31 files changed, 278757 insertions, 16 deletions
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 1d1ac1ef94f7..70e8c20acb2f 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -48,6 +48,7 @@ enum amd_asic_type { CHIP_POLARIS11, CHIP_POLARIS12, CHIP_VEGA10, + CHIP_RAVEN, CHIP_LAST, }; @@ -75,8 +76,7 @@ enum amd_ip_block_type { AMD_IP_BLOCK_TYPE_UVD, AMD_IP_BLOCK_TYPE_VCE, AMD_IP_BLOCK_TYPE_ACP, - AMD_IP_BLOCK_TYPE_GFXHUB, - AMD_IP_BLOCK_TYPE_MMHUB + AMD_IP_BLOCK_TYPE_VCN }; enum amd_clockgating_state { @@ -184,6 +184,7 @@ enum amd_fan_ctrl_mode { #define AMD_PG_SUPPORT_SAMU (1 << 10) #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) +#define AMD_PG_SUPPORT_MMHUB (1 << 13) enum amd_pm_state_type { /* not used for dpm */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h index 9a4d4c299d5b..abe05bc80752 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h @@ -906,6 +906,8 @@ #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x00000000 #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x000000ffL #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK 0x00000100L +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN__SHIFT 0x00000008 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h new file mode 100644 index 000000000000..eac125c9e300 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h @@ -0,0 +1,7988 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_1_0_DEFAULT_HEADER +#define _dcn_1_0_DEFAULT_HEADER + + +// addressBlock: dce_dc_hda_azcontroller_azdec +#define smnAZCONTROLLER0_GLOBAL_CAPABILITIES_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_MINOR_VERSION_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_MAJOR_VERSION_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_GLOBAL_CONTROL_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_WAKE_ENABLE_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_STATE_CHANGE_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_GLOBAL_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_WALL_CLOCK_COUNTER_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_STREAM_SYNCHRONIZATION_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_WRITE_POINTER_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_READ_POINTER_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_CONTROL_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_CORB_SIZE_DEFAULT 0x00000002 +#define smnAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RIRB_WRITE_POINTER_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RIRB_CONTROL_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RIRB_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_RIRB_SIZE_DEFAULT 0x00000002 +#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +#define smnAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define smnAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +#define smnAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define smnAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azroot_azdec +#define smnAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define smnAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream0_azdec +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream1_azdec +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream2_azdec +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream3_azdec +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream4_azdec +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream5_azdec +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream6_azdec +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream7_azdec +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] +#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000 +#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] +#define mmCRTC8_IDX_DEFAULT 0x00000000 +#define mmCRTC8_DATA_DEFAULT 0x00000000 +#define mmGENFC_WT_DEFAULT 0x00000000 +#define mmGENS1_DEFAULT 0x00000000 +#define mmATTRDW_DEFAULT 0x00000000 +#define mmATTRX_DEFAULT 0x00000000 +#define mmATTRDR_DEFAULT 0x00000000 +#define mmGENMO_WT_DEFAULT 0x00000000 +#define mmGENS0_DEFAULT 0x00000000 +#define mmGENENB_DEFAULT 0x00000000 +#define mmSEQ8_IDX_DEFAULT 0x00000000 +#define mmSEQ8_DATA_DEFAULT 0x00000000 +#define mmDAC_MASK_DEFAULT 0x00000000 +#define mmDAC_R_INDEX_DEFAULT 0x00000000 +#define mmDAC_W_INDEX_DEFAULT 0x00000000 +#define mmDAC_DATA_DEFAULT 0x00000000 +#define mmGENFC_RD_DEFAULT 0x00000000 +#define mmGENMO_RD_DEFAULT 0x00000000 +#define mmGRPH8_IDX_DEFAULT 0x00000000 +#define mmGRPH8_DATA_DEFAULT 0x00000000 +#define mmCRTC8_IDX_1_DEFAULT 0x00000000 +#define mmCRTC8_DATA_1_DEFAULT 0x00000000 +#define mmGENFC_WT_1_DEFAULT 0x00000000 +#define mmGENS1_1_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azcontroller_azdec +#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000 +#define mmCORB_READ_POINTER_DEFAULT 0x00000000 +#define mmCORB_CONTROL_DEFAULT 0x00000000 +#define mmCORB_STATUS_DEFAULT 0x00000000 +#define mmCORB_SIZE_DEFAULT 0x00000002 +#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000 +#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 +#define mmRIRB_CONTROL_DEFAULT 0x00000000 +#define mmRIRB_STATUS_DEFAULT 0x00000000 +#define mmRIRB_SIZE_DEFAULT 0x00000002 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 +#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 +#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azroot_azdec +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream0_azdec +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream1_azdec +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream2_azdec +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream3_azdec +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream4_azdec +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream5_azdec +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream6_azdec +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_hda_azstream7_azdec +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f +#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f +#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000 +#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002 +#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000 +#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000 +#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000 +#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000 +#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000 +#define mmD1VGA_CONTROL_DEFAULT 0x00000000 +#define mmD2VGA_CONTROL_DEFAULT 0x00000000 +#define mmVGA_STATUS_DEFAULT 0x00000000 +#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000 +#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000 +#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000 +#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018 +#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000 +#define mmVGA_QOS_CTRL_DEFAULT 0x00000000 +#define mmD3VGA_CONTROL_DEFAULT 0x00000000 +#define mmD4VGA_CONTROL_DEFAULT 0x00000000 +#define mmD5VGA_CONTROL_DEFAULT 0x00000000 +#define mmD6VGA_CONTROL_DEFAULT 0x00000000 +#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100 + + +// addressBlock: dce_dc_dccg_dccg_dispdec +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDP_DTO_DBUF_EN_DEFAULT 0x00000000 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmREFCLK_CNTL_DEFAULT 0x00000000 +#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000 +#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000 +#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 +#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003 +#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000 +#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000 +#define mmDCCG_DS_CNTL_DEFAULT 0x00000000 +#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680 +#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600 +#define mmDPREFCLK_CNTL_DEFAULT 0x00000000 +#define mmAOMCLK0_CNTL_DEFAULT 0x00000000 +#define mmAOMCLK1_CNTL_DEFAULT 0x00000000 +#define mmAOMCLK2_CNTL_DEFAULT 0x00000000 +#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000 +#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001 +#define mmDCE_VERSION_DEFAULT 0x00000000 +#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000 +#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000 +#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000 +#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000 +#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000 +#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000 +#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000 +#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000 +#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000 +#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000 +#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000 +#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000 +#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0 +#define mmDISPCLK_FREQ_CHANGE_CNTL_ |