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path: root/drivers/gpu/drm/i915/display/intel_cursor.c
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Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cursor.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_cursor.c102
1 files changed, 80 insertions, 22 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 23a122ee20c9..66436e526021 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -14,6 +14,7 @@
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_cursor.h"
+#include "intel_cursor_regs.h"
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_types.h"
@@ -293,17 +294,17 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
if (plane->cursor.base != base ||
plane->cursor.size != size ||
plane->cursor.cntl != cntl) {
- intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
- intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
- intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
- intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
- intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
+ intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0);
+ intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base);
+ intel_de_write_fw(dev_priv, CURSIZE(dev_priv, PIPE_A), size);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos);
+ intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl);
plane->cursor.base = base;
plane->cursor.size = size;
plane->cursor.cntl = cntl;
} else {
- intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos);
}
}
@@ -326,7 +327,7 @@ static bool i845_cursor_get_hw_state(struct intel_plane *plane,
if (!wakeref)
return false;
- ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
+ ret = intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & CURSOR_ENABLE;
*pipe = PIPE_A;
@@ -506,7 +507,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
}
static void wa_16021440873(struct intel_plane *plane,
@@ -521,10 +522,10 @@ static void wa_16021440873(struct intel_plane *plane,
ctl &= ~MCURSOR_MODE_MASK;
ctl |= MCURSOR_MODE_64_2B;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
- intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
- PIPESRC_HEIGHT(et_y_position));
+ intel_de_write(dev_priv, CURPOS_ERLY_TPT(dev_priv, pipe),
+ CURSOR_POS_Y(et_y_position));
}
static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
@@ -541,10 +542,12 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
if (crtc_state->enable_psr2_su_region_et) {
u32 val = intel_cursor_position(crtc_state, plane_state,
true);
- intel_de_write_fw(dev_priv, CURPOS_ERLY_TPT(pipe), val);
+ intel_de_write_fw(dev_priv,
+ CURPOS_ERLY_TPT(dev_priv, pipe),
+ val);
}
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
plane_state->ctl);
} else {
/* Wa_16021440873 */
@@ -555,6 +558,60 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
}
}
+static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
+{
+ if (!entry->end)
+ return 0;
+
+ return CUR_BUF_END(entry->end - 1) |
+ CUR_BUF_START(entry->start);
+}
+
+static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)
+{
+ u32 val = 0;
+
+ if (level->enable)
+ val |= CUR_WM_EN;
+ if (level->ignore_lines)
+ val |= CUR_WM_IGNORE_LINES;
+ val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);
+ val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);
+
+ return val;
+}
+
+static void skl_write_cursor_wm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ const struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb[plane_id];
+ int level;
+
+ for (level = 0; level < i915->display.wm.num_levels; level++)
+ intel_de_write_fw(i915, CUR_WM(pipe, level),
+ skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+
+ intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
+ skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
+
+ if (HAS_HW_SAGV_WM(i915)) {
+ const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+ intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
+ skl_cursor_wm_reg_val(&wm->sagv.wm0));
+ intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
+ skl_cursor_wm_reg_val(&wm->sagv.trans_wm));
+ }
+
+ intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
+ skl_cursor_ddb_reg_val(ddb));
+}
+
/* TODO: split into noarm+arm pair */
static void i9xx_cursor_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -611,18 +668,19 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,
plane->cursor.size != fbc_ctl ||
plane->cursor.cntl != cntl) {
if (HAS_CUR_FBC(dev_priv))
- intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
+ intel_de_write_fw(dev_priv,
+ CUR_FBC_CTL(dev_priv, pipe),
fbc_ctl);
- intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
- intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
- intel_de_write_fw(dev_priv, CURBASE(pipe), base);
+ intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);
+ intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
plane->cursor.base = base;
plane->cursor.size = fbc_ctl;
plane->cursor.cntl = cntl;
} else {
- intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
- intel_de_write_fw(dev_priv, CURBASE(pipe), base);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);
+ intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
}
}
@@ -651,7 +709,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
if (!wakeref)
return false;
- val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
+ val = intel_de_read(dev_priv, CURCNTR(dev_priv, plane->pipe));
ret = val & MCURSOR_MODE_MASK;
@@ -703,12 +761,12 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
* PSR2 plane and transcoder registers can only be updated during
* vblank.
*
- * FIXME bigjoiner fastpath would be good
+ * FIXME joiner fastpath would be good
*/
if (!crtc_state->hw.active ||
intel_crtc_needs_modeset(crtc_state) ||
intel_crtc_needs_fastset(crtc_state) ||
- crtc_state->bigjoiner_pipes)
+ crtc_state->joiner_pipes)
goto slow;
/*
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-09 17:30:52 +0000