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path: root/drivers/gpu/drm/i915/display/intel_hdmi.c
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Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_hdmi.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_hdmi.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e1a1351bc94f..c6ce6bb88d7c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1212,6 +1212,30 @@ static void vlv_set_infoframes(struct intel_encoder *encoder,
&crtc_state->infoframes.hdmi);
}
+void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ struct intel_display *display = to_intel_display(encoder);
+ i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
+ crtc_state->cpu_transcoder);
+ u32 val = intel_de_read(display, reg);
+
+ if ((crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) == 0 &&
+ (val & VIDEO_DIP_ENABLE_DRM_GLK) == 0)
+ return;
+
+ val &= ~(VIDEO_DIP_ENABLE_DRM_GLK);
+
+ intel_de_write(display, reg, val);
+ intel_de_posting_read(display, reg);
+
+ intel_write_infoframe(encoder, crtc_state,
+ HDMI_INFOFRAME_TYPE_DRM,
+ &crtc_state->infoframes.drm);
+}
+
static void hsw_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,