diff options
Diffstat (limited to 'drivers/net/ethernet/microchip/lan969x')
| -rw-r--r-- | drivers/net/ethernet/microchip/lan969x/Kconfig | 5 | ||||
| -rw-r--r-- | drivers/net/ethernet/microchip/lan969x/Makefile | 13 | ||||
| -rw-r--r-- | drivers/net/ethernet/microchip/lan969x/lan969x.c | 353 | ||||
| -rw-r--r-- | drivers/net/ethernet/microchip/lan969x/lan969x.h | 65 | ||||
| -rw-r--r-- | drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c | 191 | ||||
| -rw-r--r-- | drivers/net/ethernet/microchip/lan969x/lan969x_regs.c | 222 | ||||
| -rw-r--r-- | drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c | 3843 | ||||
| -rw-r--r-- | drivers/net/ethernet/microchip/lan969x/lan969x_vcap_impl.c | 85 |
8 files changed, 0 insertions, 4777 deletions
diff --git a/drivers/net/ethernet/microchip/lan969x/Kconfig b/drivers/net/ethernet/microchip/lan969x/Kconfig deleted file mode 100644 index c5c6122ae2ec..000000000000 --- a/drivers/net/ethernet/microchip/lan969x/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -config LAN969X_SWITCH - bool "Lan969x switch driver" - depends on SPARX5_SWITCH - help - This driver supports the lan969x family of network switch devices. diff --git a/drivers/net/ethernet/microchip/lan969x/Makefile b/drivers/net/ethernet/microchip/lan969x/Makefile deleted file mode 100644 index 316405cbbc71..000000000000 --- a/drivers/net/ethernet/microchip/lan969x/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for the Microchip lan969x network device drivers. -# - -obj-$(CONFIG_SPARX5_SWITCH) += lan969x-switch.o - -lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o \ - lan969x_vcap_ag_api.o lan969x_vcap_impl.o - -# Provide include files -ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma -ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net/ethernet/microchip/lan969x/lan969x.c deleted file mode 100644 index ac37d0f74ee3..000000000000 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ /dev/null @@ -1,353 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Microchip lan969x Switch driver - * - * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. - */ - -#include "lan969x.h" - -#define LAN969X_SDLB_GRP_CNT 5 -#define LAN969X_HSCH_LEAK_GRP_CNT 4 - -static const struct sparx5_main_io_resource lan969x_main_iomap[] = { - { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ - { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ - { TARGET_GCB, 0x2010000, 1 }, /* 0xe2010000 */ - { TARGET_QS, 0x2030000, 1 }, /* 0xe2030000 */ - { TARGET_PTP, 0x2040000, 1 }, /* 0xe2040000 */ - { TARGET_ANA_ACL, 0x2050000, 1 }, /* 0xe2050000 */ - { TARGET_LRN, 0x2060000, 1 }, /* 0xe2060000 */ - { TARGET_VCAP_SUPER, 0x2080000, 1 }, /* 0xe2080000 */ - { TARGET_QSYS, 0x20a0000, 1 }, /* 0xe20a0000 */ - { TARGET_QFWD, 0x20b0000, 1 }, /* 0xe20b0000 */ - { TARGET_XQS, 0x20c0000, 1 }, /* 0xe20c0000 */ - { TARGET_VCAP_ES2, 0x20d0000, 1 }, /* 0xe20d0000 */ - { TARGET_VCAP_ES0, 0x20e0000, 1 }, /* 0xe20e0000 */ - { TARGET_ANA_AC_POL, 0x2200000, 1 }, /* 0xe2200000 */ - { TARGET_QRES, 0x2280000, 1 }, /* 0xe2280000 */ - { TARGET_EACL, 0x22c0000, 1 }, /* 0xe22c0000 */ - { TARGET_ANA_CL, 0x2400000, 1 }, /* 0xe2400000 */ - { TARGET_ANA_L3, 0x2480000, 1 }, /* 0xe2480000 */ - { TARGET_ANA_AC_SDLB, 0x2500000, 1 }, /* 0xe2500000 */ - { TARGET_HSCH, 0x2580000, 1 }, /* 0xe2580000 */ - { TARGET_REW, 0x2600000, 1 }, /* 0xe2600000 */ - { TARGET_ANA_L2, 0x2800000, 1 }, /* 0xe2800000 */ - { TARGET_ANA_AC, 0x2900000, 1 }, /* 0xe2900000 */ - { TARGET_VOP, 0x2a00000, 1 }, /* 0xe2a00000 */ - { TARGET_DEV2G5, 0x3004000, 1 }, /* 0xe3004000 */ - { TARGET_DEV10G, 0x3008000, 1 }, /* 0xe3008000 */ - { TARGET_PCS10G_BR, 0x300c000, 1 }, /* 0xe300c000 */ - { TARGET_DEV2G5 + 1, 0x3010000, 1 }, /* 0xe3010000 */ - { TARGET_DEV2G5 + 2, 0x3014000, 1 }, /* 0xe3014000 */ - { TARGET_DEV2G5 + 3, 0x3018000, 1 }, /* 0xe3018000 */ - { TARGET_DEV2G5 + 4, 0x301c000, 1 }, /* 0xe301c000 */ - { TARGET_DEV10G + 1, 0x3020000, 1 }, /* 0xe3020000 */ - { TARGET_PCS10G_BR + 1, 0x3024000, 1 }, /* 0xe3024000 */ - { TARGET_DEV2G5 + 5, 0x3028000, 1 }, /* 0xe3028000 */ - { TARGET_DEV2G5 + 6, 0x302c000, 1 }, /* 0xe302c000 */ - { TARGET_DEV2G5 + 7, 0x3030000, 1 }, /* 0xe3030000 */ - { TARGET_DEV2G5 + 8, 0x3034000, 1 }, /* 0xe3034000 */ - { TARGET_DEV10G + 2, 0x3038000, 1 }, /* 0xe3038000 */ - { TARGET_PCS10G_BR + 2, 0x303c000, 1 }, /* 0xe303c000 */ - { TARGET_DEV2G5 + 9, 0x3040000, 1 }, /* 0xe3040000 */ - { TARGET_DEV5G, 0x3044000, 1 }, /* 0xe3044000 */ - { TARGET_PCS5G_BR, 0x3048000, 1 }, /* 0xe3048000 */ - { TARGET_DEV2G5 + 10, 0x304c000, 1 }, /* 0xe304c000 */ - { TARGET_DEV2G5 + 11, 0x3050000, 1 }, /* 0xe3050000 */ - { TARGET_DEV2G5 + 12, 0x3054000, 1 }, /* 0xe3054000 */ - { TARGET_DEV10G + 3, 0x3058000, 1 }, /* 0xe3058000 */ - { TARGET_PCS10G_BR + 3, 0x305c000, 1 }, /* 0xe305c000 */ - { TARGET_DEV2G5 + 13, 0x3060000, 1 }, /* 0xe3060000 */ - { TARGET_DEV5G + 1, 0x3064000, 1 }, /* 0xe3064000 */ - { TARGET_PCS5G_BR + 1, 0x3068000, 1 }, /* 0xe3068000 */ - { TARGET_DEV2G5 + 14, 0x306c000, 1 }, /* 0xe306c000 */ - { TARGET_DEV2G5 + 15, 0x3070000, 1 }, /* 0xe3070000 */ - { TARGET_DEV2G5 + 16, 0x3074000, 1 }, /* 0xe3074000 */ - { TARGET_DEV10G + 4, 0x3078000, 1 }, /* 0xe3078000 */ - { TARGET_PCS10G_BR + 4, 0x307c000, 1 }, /* 0xe307c000 */ - { TARGET_DEV2G5 + 17, 0x3080000, 1 }, /* 0xe3080000 */ - { TARGET_DEV5G + 2, 0x3084000, 1 }, /* 0xe3084000 */ - { TARGET_PCS5G_BR + 2, 0x3088000, 1 }, /* 0xe3088000 */ - { TARGET_DEV2G5 + 18, 0x308c000, 1 }, /* 0xe308c000 */ - { TARGET_DEV2G5 + 19, 0x3090000, 1 }, /* 0xe3090000 */ - { TARGET_DEV2G5 + 20, 0x3094000, 1 }, /* 0xe3094000 */ - { TARGET_DEV10G + 5, 0x3098000, 1 }, /* 0xe3098000 */ - { TARGET_PCS10G_BR + 5, 0x309c000, 1 }, /* 0xe309c000 */ - { TARGET_DEV2G5 + 21, 0x30a0000, 1 }, /* 0xe30a0000 */ - { TARGET_DEV5G + 3, 0x30a4000, 1 }, /* 0xe30a4000 */ - { TARGET_PCS5G_BR + 3, 0x30a8000, 1 }, /* 0xe30a8000 */ - { TARGET_DEV2G5 + 22, 0x30ac000, 1 }, /* 0xe30ac000 */ - { TARGET_DEV2G5 + 23, 0x30b0000, 1 }, /* 0xe30b0000 */ - { TARGET_DEV2G5 + 24, 0x30b4000, 1 }, /* 0xe30b4000 */ - { TARGET_DEV10G + 6, 0x30b8000, 1 }, /* 0xe30b8000 */ - { TARGET_PCS10G_BR + 6, 0x30bc000, 1 }, /* 0xe30bc000 */ - { TARGET_DEV2G5 + 25, 0x30c0000, 1 }, /* 0xe30c0000 */ - { TARGET_DEV10G + 7, 0x30c4000, 1 }, /* 0xe30c4000 */ - { TARGET_PCS10G_BR + 7, 0x30c8000, 1 }, /* 0xe30c8000 */ - { TARGET_DEV2G5 + 26, 0x30cc000, 1 }, /* 0xe30cc000 */ - { TARGET_DEV10G + 8, 0x30d0000, 1 }, /* 0xe30d0000 */ - { TARGET_PCS10G_BR + 8, 0x30d4000, 1 }, /* 0xe30d4000 */ - { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ - { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ - { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ - { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ - { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ - { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ -}; - -static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = { - { 1000000000, 8192 / 2, 64 }, /* 1 G */ - { 500000000, 8192 / 2, 64 }, /* 500 M */ - { 100000000, 8192 / 4, 64 }, /* 100 M */ - { 50000000, 8192 / 4, 64 }, /* 50 M */ - { 5000000, 8192 / 8, 64 }, /* 10 M */ -}; - -static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] = { - 655355, 1048568, 6553550, 10485680 -}; - -static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx) -{ - return &lan969x_sdlb_groups[idx]; -} - -static u32 lan969x_get_hsch_max_group_rate(int grp) -{ - return lan969x_hsch_max_group_rate[grp]; -} - -static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) -{ - if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port)) - return port; - - /* 10G */ - switch (port) { - case 0: - return 12; - case 4: - return 13; - case 8: - return 14; - case 12: - return 0; - default: - return port; - } -} - -static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) -{ - if (lan969x_port_is_5g(port)) { - switch (port) { - case 9: - return 0; - case 13: - return 1; - case 17: - return 2; - case 21: - return 3; - } - } - - if (lan969x_port_is_10g(port)) { - switch (port) { - case 0: - return 0; - case 4: - return 1; - case 8: - return 2; - case 12: - return 3; - case 16: - return 4; - case 20: - return 5; - case 24: - return 6; - case 25: - return 7; - case 26: - return 8; - case 27: - return 9; - } - } - - /* 2g5 port */ - return port; -} - -static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, - struct sparx5_port_config *conf) -{ - u32 portno = port->portno; - u32 inst; - - if (port->conf.portmode == conf->portmode) - return 0; /* Nothing to do */ - - switch (conf->portmode) { - case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q' */ - inst = (portno - portno % 4) / 4; - spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA); - break; - default: - break; - } - return 0; -} - -static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args) -{ - int budget = SPARX5_MAX_PTP_ID; - struct sparx5 *sparx5 = args; - - while (budget--) { - struct sk_buff *skb, *skb_tmp, *skb_match = NULL; - struct skb_shared_hwtstamps shhwtstamps; - struct sparx5_port *port; - struct timespec64 ts; - unsigned long flags; - u32 val, id, txport; - u32 delay; - - val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); - - /* Check if a timestamp can be retrieved */ - if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) - break; - - WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL); - - if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX)) - continue; - - /* Retrieve the ts Tx port */ - txport = PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val); - - /* Retrieve its associated skb */ - port = sparx5->ports[txport]; - - /* Retrieve the delay */ - delay = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); - delay = PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay); - - /* Get next timestamp from fifo, which needs to be the - * rx timestamp which represents the id of the frame - */ - spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), - PTP_TWOSTEP_CTRL_PTP_NXT, - sparx5, PTP_TWOSTEP_CTRL); - - val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); - - /* Check if a timestamp can be retrieved */ - if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) - break; - - /* Read RX timestamping to get the ID */ - id = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); - id <<= 8; - id |= spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS); - - spin_lock_irqsave(&port->tx_skbs.lock, flags); - skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { - if (SPARX5_SKB_CB(skb)->ts_id != id) - continue; - - __skb_unlink(skb, &port->tx_skbs); - skb_match = skb; - break; - } - spin_unlock_irqrestore(&port->tx_skbs.lock, flags); - - /* Next ts */ - spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), - PTP_TWOSTEP_CTRL_PTP_NXT, - sparx5, PTP_TWOSTEP_CTRL); - - if (WARN_ON(!skb_match)) - continue; - - spin_lock(&sparx5->ptp_ts_id_lock); - sparx5->ptp_skbs--; - spin_unlock(&sparx5->ptp_ts_id_lock); - - /* Get the h/w timestamp */ - sparx5_get_hwtimestamp(sparx5, &ts, delay); - - /* Set the timestamp in the skb */ - shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); - skb_tstamp_tx(skb_match, &shhwtstamps); - - dev_kfree_skb_any(skb_match); - } - - return IRQ_HANDLED; -} - -static const struct sparx5_regs lan969x_regs = { - .tsize = lan969x_tsize, - .gaddr = lan969x_gaddr, - .gcnt = lan969x_gcnt, - .gsize = lan969x_gsize, - .raddr = lan969x_raddr, - .rcnt = lan969x_rcnt, - .fpos = lan969x_fpos, - .fsize = lan969x_fsize, -}; - -static const struct sparx5_consts lan969x_consts = { - .n_ports = 30, - .n_ports_all = 35, - .n_hsch_l1_elems = 32, - .n_hsch_queues = 4, - .n_lb_groups = 5, - .n_pgids = 1054, /* (1024 + n_ports) */ - .n_sio_clks = 1, - .n_own_upsids = 1, - .n_auto_cals = 4, - .n_filters = 256, - .n_gates = 256, - .n_sdlbs = 496, - .n_dsm_cal_taxis = 5, - .buf_size = 1572864, - .qres_max_prio_idx = 315, - .qres_max_colour_idx = 323, - .tod_pin = 4, - .vcaps = lan969x_vcaps, - .vcap_stats = &lan969x_vcap_stats, - .vcaps_cfg = lan969x_vcap_inst_cfg, -}; - -static const struct sparx5_ops lan969x_ops = { - .is_port_2g5 = &lan969x_port_is_2g5, - .is_port_5g = &lan969x_port_is_5g, - .is_port_10g = &lan969x_port_is_10g, - .is_port_25g = &lan969x_port_is_25g, - .get_port_dev_index = &lan969x_port_dev_mapping, - .get_port_dev_bit = &lan969x_get_dev_mode_bit, - .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, - .get_sdlb_group = &lan969x_get_sdlb_group, - .set_port_mux = &lan969x_port_mux_set, - .ptp_irq_handler = &lan969x_ptp_irq_handler, - .dsm_calendar_calc = &lan969x_dsm_calendar_calc, -}; - -const struct sparx5_match_data lan969x_desc = { - .iomap = lan969x_main_iomap, - .iomap_size = ARRAY_SIZE(lan969x_main_iomap), - .ioranges = 2, - .regs = &lan969x_regs, - .consts = &lan969x_consts, - .ops = &lan969x_ops, -}; -EXPORT_SYMBOL_GPL(lan969x_desc); - -MODULE_DESCRIPTION("Microchip lan969x switch driver"); -MODULE_AUTHOR("Daniel Machon <daniel.machon@microchip.com>"); -MODULE_LICENSE("Dual MIT/GPL"); diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.h b/drivers/net/ethernet/microchip/lan969x/lan969x.h deleted file mode 100644 index 2489d0d32dfd..000000000000 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* Microchip lan969x Switch driver - * - * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. - */ - -#ifndef __LAN969X_H__ -#define __LAN969X_H__ - -#include "../sparx5/sparx5_main.h" -#include "../sparx5/sparx5_regs.h" -#include "../sparx5/sparx5_vcap_impl.h" - -/* lan969x.c */ -extern const struct sparx5_match_data lan969x_desc; - -/* lan969x_vcap_ag_api.c */ -extern const struct vcap_statistics lan969x_vcap_stats; -extern const struct vcap_info lan969x_vcaps[]; - -/* lan969x_vcap_impl.c */ -extern const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[]; - -/* lan969x_regs.c */ -extern const unsigned int lan969x_tsize[TSIZE_LAST]; -extern const unsigned int lan969x_raddr[RADDR_LAST]; -extern const unsigned int lan969x_rcnt[RCNT_LAST]; -extern const unsigned int lan969x_gaddr[GADDR_LAST]; -extern const unsigned int lan969x_gcnt[GCNT_LAST]; -extern const unsigned int lan969x_gsize[GSIZE_LAST]; -extern const unsigned int lan969x_fpos[FPOS_LAST]; -extern const unsigned int lan969x_fsize[FSIZE_LAST]; - -static inline bool lan969x_port_is_2g5(int portno) -{ - return portno == 1 || portno == 2 || portno == 3 || - portno == 5 || portno == 6 || portno == 7 || - portno == 10 || portno == 11 || portno == 14 || - portno == 15 || portno == 18 || portno == 19 || - portno == 22 || portno == 23; -} - -static inline bool lan969x_port_is_5g(int portno) -{ - return portno == 9 || portno == 13 || portno == 17 || - portno == 21; -} - -static inline bool lan969x_port_is_10g(int portno) -{ - return portno == 0 || portno == 4 || portno == 8 || - portno == 12 || portno == 16 || portno == 20 || - portno == 24 || portno == 25 || portno == 26 || - portno == 27; -} - -static inline bool lan969x_port_is_25g(int portno) -{ - return false; -} - -/* lan969x_calendar.c */ -int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, - struct sparx5_calendar_data *data); -#endif diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c b/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c deleted file mode 100644 index e857640df185..000000000000 --- a/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Microchip lan969x Switch driver - * - * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. - */ - -#include "lan969x.h" - -#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10 -#define LAN969X_DSM_CAL_TAXIS 5 - -enum lan969x_dsm_cal_dev { - DSM_CAL_DEV_2G5, - DSM_CAL_DEV_5G, - DSM_CAL_DEV_10G, - DSM_CAL_DEV_OTHER, /* 1G or less */ - DSM_CAL_DEV_MAX -}; - -/* Each entry in the following struct defines properties for a given speed - * (10G, 5G, 2.5G, or 1G or less). - */ -struct lan969x_dsm_cal_dev_speed { - /* Number of devices that requires this speed. */ - u32 n_devs; - - /* Array of devices that requires this speed. */ - u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI]; - - /* Number of slots required for one device running this speed. */ - u32 n_slots; - - /* Gap between two slots for one device running this speed. */ - u32 gap; -}; - -static u32 -lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = { - { 0, 4, 1, 2, 3, 5, 6, 7, 28, 29 }, - { 8, 12, 9, 13, 10, 11, 14, 15, 99, 99 }, - { 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 }, - { 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 }, - { 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 } -}; - -static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_idx) -{ - if (*cal_idx >= cal_len) - return -EINVAL; - - do { - if (calendar[*cal_idx] == SPX5_DSM_CAL_EMPTY) - return 0; - - (*cal_idx)++; - } while (*cal_idx < cal_len); - - return -ENOENT; -} - -static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed) -{ - return (speed == 10000 ? DSM_CAL_DEV_10G : - speed == 5000 ? DSM_CAL_DEV_5G : - speed == 2500 ? DSM_CAL_DEV_2G5 : - DSM_CAL_DEV_OTHER); -} - -static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev) -{ - return (dev == DSM_CAL_DEV_10G ? 10000 : - dev == DSM_CAL_DEV_5G ? 5000 : - dev == DSM_CAL_DEV_2G5 ? 2500 : - 1000); -} - -int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, - struct sparx5_calendar_data *data) -{ - struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] = {}; - u32 cal_len, n_slots, taxi_bw, n_devs = 0, required_bw = 0; - struct lan969x_dsm_cal_dev_speed *speed; - int err; - - /* Maximum bandwidth for this taxi */ - taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); - - memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi], - LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32)); - - for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { - u32 portno = data->taxi_ports[i]; - enum sparx5_cal_bw bw; - - bw = sparx5_get_port_cal_speed(sparx5, portno); - - if (portno < sparx5->data->consts->n_ports_all) - data->taxi_speeds[i] = sparx5_cal_speed_to_value(bw); - else - data->taxi_speeds[i] = 0; - } - - /* Determine the different port types (10G, 5G, 2.5G, <= 1G) in the - * this taxi map. - */ - for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { - u32 taxi_speed = data->taxi_speeds[i]; - enum lan969x_dsm_cal_dev dev; - - if (taxi_speed == 0) - continue; - - required_bw += taxi_speed; - - dev = lan969x_dsm_cal_get_dev(taxi_speed); - speed = &dev_speeds[dev]; - speed->devs[speed->n_devs++] = i; - n_devs++; - } - - if (required_bw > taxi_bw) { - pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u", - required_bw, taxi_bw); - return -EINVAL; - } - - if (n_devs == 0) { - data->schedule[0] = SPX5_DSM_CAL_EMPTY; - return 0; - } - - cal_len = n_devs; - - /* Search for a calendar length that fits all active devices. */ - while (cal_len < SPX5_DSM_CAL_LEN) { - u32 bw_per_slot = taxi_bw / cal_len; - - n_slots = 0; - - for (int i = 0; i < DSM_CAL_DEV_MAX; i++) { - speed = &dev_speeds[i]; - - if (speed->n_devs == 0) - continue; - - required_bw = lan969x_dsm_cal_get_speed(i); - speed->n_slots = DIV_ROUND_UP(required_bw, bw_per_slot); - - if (speed->n_slots) - speed->gap = DIV_ROUND_UP(cal_len, - speed->n_slots); - else - speed->gap = 0; - - n_slots += speed->n_slots * speed->n_devs; - } - - if (n_slots <= cal_len) - break; /* Found a suitable calendar length. */ - - /* Not good enough yet. */ - cal_len = n_slots; - } - - if (cal_len > SPX5_DSM_CAL_LEN) { - pr_err("Invalid length: %u for taxi: %u", cal_len, taxi); - return -EINVAL; - } - - for (u32 i = 0; i < SPX5_DSM_CAL_LEN; i++) - data->schedule[i] = SPX5_DSM_CAL_EMPTY; - - /* Place the remaining devices */ - for (u32 i = 0; i < DSM_CAL_DEV_MAX; i++) { - speed = &dev_speeds[i]; - for (u32 dev = 0; dev < speed->n_devs; dev++) { - u32 idx = 0; - - for (n_slots = 0; n_slots < speed->n_slots; n_slots++) { - err = lan969x_dsm_cal_idx_get(data->schedule, - cal_len, &idx); - if (err) - return err; - data->schedule[idx] = speed->devs[dev]; - idx += speed->gap; - } - } - } - - return 0; -} diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c b/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c deleted file mode 100644 index ace4ba21eec4..000000000000 --- a/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c +++ /dev/null @@ -1,222 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Microchip lan969x Switch driver - * - * Copyright (c) 2024 Microchip Technology Inc. - */ - -/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. - * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b - */ - -#include "lan969x.h" - -const unsigned int lan969x_tsize[TSIZE_LAST] = { - [TC_DEV10G] = 10, - [TC_DEV2G5] = 28, - [TC_DEV5G] = 4, - [TC_PCS10G_BR] = 10, - [TC_PCS5G_BR] = 4, -}; - -const unsigned int lan969x_raddr[RADDR_LAST] = { - [RA_CPU_PROC_CTRL] = 160, - [RA_GCB_SOFT_RST] = 12, - [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20, -}; - -const unsigned int lan969x_rcnt[RCNT_LAST] = { - [RC_ANA_AC_OWN_UPSID] = 1, - [RC_ANA_ACL_VCAP_S2_CFG] = 35, - [RC_ANA_ACL_OWN_UPSID] = 1, - [RC_ANA_CL_OWN_UPSID] = 1, - [RC_ANA_L2_OWN_UPSID] = 1, - [RC_ASM_PORT_CFG] = 32, - [RC_DSM_BUF_CFG] = 32, - [RC_DSM_DEV_TX_STOP_WM_CFG] = 32, - [RC_DSM_RX_PAUSE_CFG] = 32, - [RC_DSM_MAC_CFG] = 32, - [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30, - [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30, - [RC_DSM_TAXI_CAL_CFG] = 6, - [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30, - [RC_HSCH_PORT_MODE] = 35, - [RC_QFWD_SWITCH_PORT_MODE] = 35, - [RC_QSYS_PAUSE_CFG] = 35, - [RC_QSYS_ATOP] = 35, - [RC_QSYS_FWD_PRESSURE] = 35, - [RC_QSYS_CAL_AUTO] = 4, - [RC_REW_OWN_UPSID] = 1, - [RC_REW_RTAG_ETAG_CTRL] = 35, -}; - -const unsigned int lan969x_gaddr[GADDR_LAST] = { - [GA_ANA_AC_RAM_CTRL] = 202000, - [GA_ANA_AC_PS_COMMON] = 202880, - [GA_ANA_AC_MIRROR_PROBE] = 203232, - [GA_ANA_AC_SRC] = 201728, - [GA_ANA_AC_PGID] = 131072, - [GA_ANA_AC_TSN_SF] = 202028, - [GA_ANA_AC_TSN_SF_CFG] = 148480, - [GA_ANA_AC_TSN_SF_STATUS] = 147936, - [GA_ANA_AC_SG_ACCESS] = 202032, - [GA_ANA_AC_SG_CONFIG] = 202752, - [GA_ANA_AC_SG_STATUS] = 147952, - [GA_ANA_AC_SG_STATUS_STICKY] = 202044, - [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048, - [GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800, - [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068, - [GA_ANA_ACL_COMMON] = 8192, - [GA_ANA_ACL_KEY_SEL] = 9204, - [GA_ANA_ACL_CNT_B] = 4096, - [GA_ANA_ACL_STICKY] = 10852, - [GA_ANA_AC_POL_POL_ALL_CFG] = 17504, - [GA_ANA_AC_POL_COMMON_BDLB] = 19464, - [GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472, - [GA_ANA_AC_SDLB_LBGRP_TBL] = 31788, - [GA_ANA_CL_PORT] = 65536, - [GA_ANA_CL_COMMON] = 87040, - [GA_ANA_L2_COMMON] = 561928, - [GA_ANA_L3_COMMON] = 370752, - [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580, - [GA_ASM_CFG] = 18304, - [GA_ASM_PFC_TIMER_CFG] = 15568, - [GA_ASM_LBK_WM_CFG] = 15596, - [GA_ASM_LBK_MISC_CFG] = 15608, - [GA_ASM_RAM_CTRL] = 15684, - [GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864, - [GA_EACL_CNT_TBL] = 30720, - [GA_EACL_POL_CFG] = 38400, - [GA_EACL_ES2_STICKY] = 29072, - [GA_EACL_RAM_CTRL] = 29112, - [GA_GCB_SIO_CTRL] = 560, - [GA_HSCH_HSCH_DWRR] = 36480, - [GA_HSCH_HSCH_MISC] = 36608, - [GA_HSCH_HSCH_LEAK_LISTS] = 37256, - [GA_HSCH_SYSTEM] = 37384, - [GA_HSCH_MMGT] = 36260, - [GA_HSCH_TAS_CONFIG] = 37696, - [GA_PTP_PTP_CFG] = 512, - [GA_PTP_PTP_TOD_DOMAINS] = 528, - [GA_PTP_PHASE_DETECTOR_CTRL] = 628, - [GA_QSYS_CALCFG] = 2164, - [GA_QSYS_RAM_CTRL] = 2204, - [GA_REW_COMMON] = 98304, - [GA_REW_PORT] = 49152, - [GA_REW_VOE_PORT_LM_CNT] = 90112, - [GA_REW_RAM_CTRL] = 93992, - [GA_VOP_RAM_CTRL] = 16368, - [GA_XQS_SYSTEM] = 5744, - [GA_XQS_QLIMIT_SHR] = 6912, -}; - -const unsigned int lan969x_gcnt[GCNT_LAST] = { - [GC_ANA_AC_SRC] = 67, - [GC_ANA_AC_PGID] = 1054, - [GC_ANA_AC_TSN_SF_CFG] = 256, - [GC_ANA_AC_STAT_CNT_CFG_PORT] = 35, - [GC_ANA_ACL_KEY_SEL] = 99, - [GC_ANA_ACL_CNT_A] = 1024, - [GC_ANA_ACL_CNT_B] = 1024, - [GC_ANA_AC_SDLB_LBGRP_TBL] = 5, - [GC_ANA_AC_SDLB_LBSET_TBL] = 496, - [GC_ANA_CL_PORT] = 35, - [GC_ANA_L2_ISDX_LIMIT] = 256, - [GC_ANA_L2_ISDX] = 1024, - [GC_ANA_L3_VLAN] = 4608, - [GC_ASM_DEV_STATISTICS] = 30, - [GC_EACL_ES2_KEY_SELECT_PROFILE] = 68, - [GC_EACL_CNT_TBL] = 512, - [GC_GCB_SIO_CTRL] = 1, - [GC_HSCH_HSCH_CFG] = 1120, - [GC_HSCH_HSCH_DWRR] = 32, - [GC_PTP_PTP_PINS] = 8, - [GC_PTP_PHASE_DETECTOR_CTRL] = 8, - [GC_REW_PORT] = 35, - [GC_REW_VOE_PORT_LM_CNT] = 240, -}; - -const unsigned int lan969x_gsize[GSIZE_LAST] = { - [GW_ANA_AC_SRC] = 4, - [GW_ANA_L2_COMMON] = 712, - [GW_ASM_CFG] = 1092, - [GW_CPU_CPU_REGS] = 180, - [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12, - [GW_FDMA_FDMA] = 448, - [GW_GCB_CHIP_REGS] = 180, - [GW_HSCH_TAS_CONFIG] = 16, - [GW_PTP_PHASE_DETECTOR_CTRL] = 12, - [GW_QSYS_PAUSE_CFG] = 988, -}; - -const unsigned int lan969x_fpos[FPOS_LAST] = { - [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7, - [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6, - [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5, - [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4, - [FP_CPU_PROC_CTRL_VINITHI] = 3, - [FP_CPU_PROC_CTRL_CFGTE] = 2, - [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1, - [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0, - [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8, - [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5, - [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3, - [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5, - [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4, - [FP_FDMA_CH_CFG_CH_INJ_PORT] = 3, - [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27, - [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25, - [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24, - [FP_PTP_PHAD_CTRL_PHAD_ENA] = 5, - [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3, -}; - -const unsigned int lan969x_fsize[FSIZE_LAST] = { - [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30, - [FW_ANA_AC_SRC_CFG_PORT_MASK] = 30, - [FW_ANA_AC_PGID_CFG_PORT_MASK] = 30, - [FW_ANA_AC_TSN_SF_PORT_NUM] = 7, - [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8, - [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8, - [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8, - [FW_ANA_AC_PORT_SGE_CFG_MASK] = 17, - [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9, - [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3, - [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9, - [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9, - [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3, - [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9, - [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30, - [FW_ANA_L2_DLB_CFG_DLB_IDX] = 9, - [FW_ANA_L2_TSN_CFG_TSN_SFID] = 8, - [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30, - [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2, - [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7, - [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5, - [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14, - [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6, - [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11, - [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14, - [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6, - [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14, - [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13, - [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8, - [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13, - [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8, - [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8, - [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8, - [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3, - [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6, - [FW_QRES_RES_CFG_WM_HIGH] = 11, - [FW_QRES_RES_STAT_MAXUSE] = 19, - [FW_QRES_RES_STAT_CUR_INUSE] = 19, - [FW_QSYS_PAUSE_CFG_PAUSE_START] = 11, - [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11, - [FW_QSYS_ATOP_ATOP] = 11, - [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11, - [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6, - [FW_XQS_STAT_CFG_STAT_VIEW] = 10, - [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14, - [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14, - [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14, - [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14, -}; diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c b/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c deleted file mode 100644 index 7acc5bcf337a..000000000000 --- a/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c +++ /dev/null @@ -1,3843 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. - * Microchip VCAP API - */ - -/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200. - * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391 - */ - -#include <linux/types.h> -#include <linux/kernel.h> - -#include "lan969x.h" - -/* keyfields */ -static const struct vcap_field is0_normal_7tuple_keyfield[] = { - [VCAP_KF_TYPE] = { - .type = VCAP_FIELD_BIT, - .offset = 0, - .width = 1, - }, - [VCAP_KF_LOOKUP_FIRST_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 1, - .width = 1, - }, - [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 2, - .width = 2, - }, - [VCAP_KF_LOOKUP_GEN_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 4, - .width = 10, - }, - [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 14, - .width = 2, - }, - [VCAP_KF_IF_IGR_PORT_MASK] = { - .type = VCAP_FIELD_U72, - .offset = 16, - .width = 65, - }, - [VCAP_KF_L2_MC_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 81, - .width = 1, - }, - [VCAP_KF_L2_BC_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 82, - .width = 1, - }, - [VCAP_KF_8021Q_VLAN_TAGS] = { - .type = VCAP_FIELD_U32, - .offset = 83, - .width = 3, - }, - [VCAP_KF_8021Q_TPID0] = { - .type = VCAP_FIELD_U32, - .offset = 86, - .width = 3, - }, - [VCAP_KF_8021Q_PCP0] = { - .type = VCAP_FIELD_U32, - .offset = 89, - .width = 3, - }, - [VCAP_KF_8021Q_DEI0] = { - .type = VCAP_FIELD_BIT, - .offset = 92, - .width = 1, - }, - [VCAP_KF_8021Q_VID0] = { - .type = VCAP_FIELD_U32, - .offset = 93, - .width = 12, - }, - [VCAP_KF_8021Q_TPID1] = { - .type = VCAP_FIELD_U32, - .offset = 105, - .width = 3, - }, - [VCAP_KF_8021Q_PCP1] = { - .type = VCAP_FIELD_U32, - .offset = 108, - .width = 3, - }, - [VCAP_KF_8021Q_DEI1] = { - .type = VCAP_FIELD_BIT, - .offset = 111, - .width = 1, - }, - [VCAP_KF_8021Q_VID1] = { - .type = VCAP_FIELD_U32, - .offset = 112, - .width = 12, - }, - [VCAP_KF_8021Q_TPID2] = { - .type = VCAP_FIELD_U32, - .offset = 124, - .width = 3, - }, - [VCAP_KF_8021Q_PCP2] = { - .type = VCAP_FIELD_U32, - .offset = 127, - .width = 3, - }, - [VCAP_KF_8021Q_DEI2] = { - .type = VCAP_FIELD_BIT, - .offset = 130, - .width = 1, - }, - [VCAP_KF_8021Q_VID2] = { - .type = VCAP_FIELD_U32, - .offset = 131, - .width = 12, - }, - [VCAP_KF_L2_DMAC] = { - .type = VCAP_FIELD_U48, - .offset = 144, - .width = 48, - }, - [VCAP_KF_L2_SMAC] = { - .type = VCAP_FIELD_U48, - .offset = 192, - .width = 48, - }, - [VCAP_KF_IP_MC_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 240, - .width = 1, - }, - [VCAP_KF_ETYPE_LEN_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 241, - .width = 1, - }, - [VCAP_KF_ETYPE] = { - .type = VCAP_FIELD_U32, - .offset = 242, - .width = 16, - }, - [VCAP_KF_IP_SNAP_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 258, - .width = 1, - }, - [VCAP_KF_IP4_IS] = { |