diff options
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp.h | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index adb155a45923..6cb660455088 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -64,46 +64,6 @@ #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 -/* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */ - -#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c -#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 -#define QSERDES_TX0_LANE_MODE_1 0x084 -#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c - -/* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */ - -#define QSERDES_RX0_UCDR_FO_GAIN 0x008 -#define QSERDES_RX0_UCDR_SO_GAIN 0x014 -#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034 -#define QSERDES_RX0_UCDR_PI_CONTROLS 0x044 -#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec -#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0 -#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4 -#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8 -#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc -#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 -#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114 -#define QSERDES_RX0_SIGDET_ENABLES 0x118 -#define QSERDES_RX0_SIGDET_CNTRL 0x11c -#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124 -#define QSERDES_RX0_RX_MODE_00_LOW 0x170 -#define QSERDES_RX0_RX_MODE_00_HIGH 0x174 -#define QSERDES_RX0_RX_MODE_00_HIGH2 0x178 -#define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c -#define QSERDES_RX0_RX_MODE_00_HIGH4 0x180 -#define QSERDES_RX0_RX_MODE_01_LOW 0x184 -#define QSERDES_RX0_RX_MODE_01_HIGH 0x188 -#define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c -#define QSERDES_RX0_RX_MODE_01_HIGH3 0x190 -#define QSERDES_RX0_RX_MODE_01_HIGH4 0x194 -#define QSERDES_RX0_RX_MODE_10_LOW 0x198 -#define QSERDES_RX0_RX_MODE_10_HIGH 0x19c -#define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0 -#define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4 -#define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8 -#define QSERDES_RX0_DFE_EN_TIMER 0x1b4 - /* QMP V2 PHY for PCIE gen3 ports - PCS registers */ #define PCS_COM_FLL_CNTRL1 0x098 |