diff options
Diffstat (limited to 'drivers')
37 files changed, 3185 insertions, 278 deletions
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 3b205e212337..7010dcac9328 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -108,6 +108,14 @@ config OMAP_OCP2SCP OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via OCP2SCP. +config QCOM_EBI2 + bool "Qualcomm External Bus Interface 2 (EBI2)" + depends on HAS_IOMEM + help + Say y here to enable support for the Qualcomm External Bus + Interface 2, which can be used to connect things like NAND Flash, + SRAM, ethernet adapters, FPGAs and LCD displays. + config SIMPLE_PM_BUS bool "Simple Power-Managed Bus Driver" depends on OF && PM @@ -132,12 +140,8 @@ config SUNXI_RSB with various RSB based devices, such as AXP223, AXP8XX PMICs, and AC100/AC200 ICs. -# TODO: This uses pm_clk_*() symbols that aren't exported in v4.7 and hence -# the driver will fail to build as a module. However there are patches to -# address that queued for v4.8, so this can be turned into a tristate symbol -# after v4.8-rc1. config TEGRA_ACONNECT - bool "Tegra ACONNECT Bus Driver" + tristate "Tegra ACONNECT Bus Driver" depends on ARCH_TEGRA_210_SOC depends on OF && PM select PM_CLK diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index ac84cc4348e3..c6cfa6b2606e 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o +obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o diff --git a/drivers/bus/qcom-ebi2.c b/drivers/bus/qcom-ebi2.c new file mode 100644 index 000000000000..a6444244c411 --- /dev/null +++ b/drivers/bus/qcom-ebi2.c @@ -0,0 +1,408 @@ +/* + * Qualcomm External Bus Interface 2 (EBI2) driver + * an older version of the Qualcomm Parallel Interface Controller (QPIC) + * + * Copyright (C) 2016 Linaro Ltd. + * + * Author: Linus Walleij <linus.walleij@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * See the device tree bindings for this block for more details on the + * hardware. + */ + +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/bitops.h> + +/* + * CS0, CS1, CS4 and CS5 are two bits wide, CS2 and CS3 are one bit. + */ +#define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1) +#define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3) +#define EBI2_CS2_ENABLE_MASK BIT(4) +#define EBI2_CS3_ENABLE_MASK BIT(5) +#define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7) +#define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9) +#define EBI2_CSN_MASK GENMASK(9, 0) + +#define EBI2_XMEM_CFG 0x0000 /* Power management etc */ + +/* + * SLOW CSn CFG + * + * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the + * memory continues to drive the data bus after OE is de-asserted. + * Inserted when reading one CS and switching to another CS or read + * followed by write on the same CS. Valid values 0 thru 15. + * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after + * every write minimum 1. The data out is driven from the time WE is + * asserted until CS is asserted. With a hold of 1, the CS stays + * active for 1 extra cycle etc. Valid values 0 thru 15. + * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first + * write to a page or burst memory + * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first + * read to a page or burst memory + * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle + * so 1 thru 16 cycles. + * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle + * so 1 thru 16 cycles. + */ +#define EBI2_XMEM_CS0_SLOW_CFG 0x0008 +#define EBI2_XMEM_CS1_SLOW_CFG 0x000C +#define EBI2_XMEM_CS2_SLOW_CFG 0x0010 +#define EBI2_XMEM_CS3_SLOW_CFG 0x0014 +#define EBI2_XMEM_CS4_SLOW_CFG 0x0018 +#define EBI2_XMEM_CS5_SLOW_CFG 0x001C + +#define EBI2_XMEM_RECOVERY_SHIFT 28 +#define EBI2_XMEM_WR_HOLD_SHIFT 24 +#define EBI2_XMEM_WR_DELTA_SHIFT 16 +#define EBI2_XMEM_RD_DELTA_SHIFT 8 +#define EBI2_XMEM_WR_WAIT_SHIFT 4 +#define EBI2_XMEM_RD_WAIT_SHIFT 0 + +/* + * FAST CSn CFG + * Bits 31-28: ? + * Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read + * transfer. For a single read trandfer this will be the time + * from CS assertion to OE assertion. + * Bits 18-24: ? + * Bits 17-16: ADV_OE_RECOVERY, the number of cycles elapsed before an OE + * assertion, with respect to the cycle where ADV is asserted. + * 2 means 2 cycles between ADV and OE. Values 0, 1, 2 or 3. + * Bits 5: ADDR_HOLD_ENA, The address is held for an extra cycle to meet + * hold time requirements with ADV assertion. + * + * The manual mentions "write precharge cycles" and "precharge cycles". + * We have not been able to figure out which bit fields these correspond to + * in the hardware, or what valid values exist. The current hypothesis is that + * this is something just used on the FAST chip selects. There is also a "byte + * device enable" flag somewhere for 8bit memories. + */ +#define EBI2_XMEM_CS0_FAST_CFG 0x0028 +#define EBI2_XMEM_CS1_FAST_CFG 0x002C +#define EBI2_XMEM_CS2_FAST_CFG 0x0030 +#define EBI2_XMEM_CS3_FAST_CFG 0x0034 +#define EBI2_XMEM_CS4_FAST_CFG 0x0038 +#define EBI2_XMEM_CS5_FAST_CFG 0x003C + +#define EBI2_XMEM_RD_HOLD_SHIFT 24 +#define EBI2_XMEM_ADV_OE_RECOVERY_SHIFT 16 +#define EBI2_XMEM_ADDR_HOLD_ENA_SHIFT 5 + +/** + * struct cs_data - struct with info on a chipselect setting + * @enable_mask: mask to enable the chipselect in the EBI2 config + * @slow_cfg0: offset to XMEMC slow CS config + * @fast_cfg1: offset to XMEMC fast CS config + */ +struct cs_data { + u32 enable_mask; + u16 slow_cfg; + u16 fast_cfg; +}; + +static const struct cs_data cs_info[] = { + { + /* CS0 */ + .enable_mask = EBI2_CS0_ENABLE_MASK, + .slow_cfg = EBI2_XMEM_CS0_SLOW_CFG, + .fast_cfg = EBI2_XMEM_CS0_FAST_CFG, + }, + { + /* CS1 */ + .enable_mask = EBI2_CS1_ENABLE_MASK, + .slow_cfg = EBI2_XMEM_CS1_SLOW_CFG, + .fast_cfg = EBI2_XMEM_CS1_FAST_CFG, + }, + { + /* CS2 */ + .enable_mask = EBI2_CS2_ENABLE_MASK, + .slow_cfg = EBI2_XMEM_CS2_SLOW_CFG, + .fast_cfg = EBI2_XMEM_CS2_FAST_CFG, + }, + { + /* CS3 */ + .enable_mask = EBI2_CS3_ENABLE_MASK, + .slow_cfg = EBI2_XMEM_CS3_SLOW_CFG, + .fast_cfg = EBI2_XMEM_CS3_FAST_CFG, + }, + { + /* CS4 */ + .enable_mask = EBI2_CS4_ENABLE_MASK, + .slow_cfg = EBI2_XMEM_CS4_SLOW_CFG, + .fast_cfg = EBI2_XMEM_CS4_FAST_CFG, + }, + { + /* CS5 */ + .enable_mask = EBI2_CS5_ENABLE_MASK, + .slow_cfg = EBI2_XMEM_CS5_SLOW_CFG, + .fast_cfg = EBI2_XMEM_CS5_FAST_CFG, + }, +}; + +/** + * struct ebi2_xmem_prop - describes an XMEM config property + * @prop: the device tree binding name + * @max: maximum value for the property + * @slowreg: true if this property is in the SLOW CS config register + * else it is assumed to be in the FAST config register + * @shift: the bit field start in the SLOW or FAST register for this + * property + */ +struct ebi2_xmem_prop { + const char *prop; + u32 max; + bool slowreg; + u16 shift; +}; + +static const struct ebi2_xmem_prop xmem_props[] = { + { + .prop = "qcom,xmem-recovery-cycles", + .max = 15, + .slowreg = true, + .shift = EBI2_XMEM_RECOVERY_SHIFT, + }, + { + .prop = "qcom,xmem-write-hold-cycles", + .max = 15, + .slowreg = true, + .shift = EBI2_XMEM_WR_HOLD_SHIFT, + }, + { + .prop = "qcom,xmem-write-delta-cycles", + .max = 255, + .slowreg = true, + .shift = EBI2_XMEM_WR_DELTA_SHIFT, + }, + { + .prop = "qcom,xmem-read-delta-cycles", + .max = 255, + .slowreg = true, + .shift = EBI2_XMEM_RD_DELTA_SHIFT, + }, + { + .prop = "qcom,xmem-write-wait-cycles", + .max = 15, + .slowreg = true, + .shift = EBI2_XMEM_WR_WAIT_SHIFT, + }, + { + .prop = "qcom,xmem-read-wait-cycles", + .max = 15, + .slowreg = true, + .shift = EBI2_XMEM_RD_WAIT_SHIFT, + }, + { + .prop = "qcom,xmem-address-hold-enable", + .max = 1, /* boolean prop */ + .slowreg = false, + .shift = EBI2_XMEM_ADDR_HOLD_ENA_SHIFT, + }, + { + .prop = "qcom,xmem-adv-to-oe-recovery-cycles", + .max = 3, + .slowreg = false, + .shift = EBI2_XMEM_ADV_OE_RECOVERY_SHIFT, + }, + { + .prop = "qcom,xmem-read-hold-cycles", + .max = 15, + .slowreg = false, + .shift = EBI2_XMEM_RD_HOLD_SHIFT, + }, +}; + +static void qcom_ebi2_setup_chipselect(struct device_node *np, + struct device *dev, + void __iomem *ebi2_base, + void __iomem *ebi2_xmem, + u32 csindex) +{ + const struct cs_data *csd; + u32 slowcfg, fastcfg; + u32 val; + int ret; + int i; + + csd = &cs_info[csindex]; + val = readl(ebi2_base); + val |= csd->enable_mask; + writel(val, ebi2_base); + dev_dbg(dev, "enabled CS%u\n", csindex); + + /* Next set up the XMEMC */ + slowcfg = 0; + fastcfg = 0; + + for (i = 0; i < ARRAY_SIZE(xmem_props); i++) { + const struct ebi2_xmem_prop *xp = &xmem_props[i]; + + /* All are regular u32 values */ + ret = of_property_read_u32(np, xp->prop, &val); + if (ret) { + dev_dbg(dev, "could not read %s for CS%d\n", + xp->prop, csindex); + continue; + } + + /* First check boolean props */ + if (xp->max == 1 && val) { + if (xp->slowreg) + slowcfg |= BIT(xp->shift); + else + fastcfg |= BIT(xp->shift); + dev_dbg(dev, "set %s flag\n", xp->prop); + continue; + } + + /* We're dealing with an u32 */ + if (val > xp->max) { + dev_err(dev, + "too high value for %s: %u, capped at %u\n", + xp->prop, val, xp->max); + val = xp->max; + } + if (xp->slowreg) + slowcfg |= (val << xp->shift); + else + fastcfg |= (val << xp->shift); + dev_dbg(dev, "set %s to %u\n", xp->prop, val); + } + + dev_info(dev, "CS%u: SLOW CFG 0x%08x, FAST CFG 0x%08x\n", + csindex, slowcfg, fastcfg); + + if (slowcfg) + writel(slowcfg, ebi2_xmem + csd->slow_cfg); + if (fastcfg) + writel(fastcfg, ebi2_xmem + csd->fast_cfg); +} + +static int qcom_ebi2_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + struct device *dev = &pdev->dev; + struct resource *res; + void __iomem *ebi2_base; + void __iomem *ebi2_xmem; + struct clk *ebi2xclk; + struct clk *ebi2clk; + bool have_children = false; + u32 val; + int ret; + + ebi2xclk = devm_clk_get(dev, "ebi2x"); + if (IS_ERR(ebi2xclk)) + return PTR_ERR(ebi2xclk); + + ret = clk_prepare_enable(ebi2xclk); + if (ret) { + dev_err(dev, "could not enable EBI2X clk (%d)\n", ret); + return ret; + } + + ebi2clk = devm_clk_get(dev, "ebi2"); + if (IS_ERR(ebi2clk)) { + ret = PTR_ERR(ebi2clk); + goto err_disable_2x_clk; + } + + ret = clk_prepare_enable(ebi2clk); + if (ret) { + dev_err(dev, "could not enable EBI2 clk\n"); + goto err_disable_2x_clk; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ebi2_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ebi2_base)) { + ret = PTR_ERR(ebi2_base); + goto err_disable_clk; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + ebi2_xmem = devm_ioremap_resource(dev, res); + if (IS_ERR(ebi2_xmem)) { + ret = PTR_ERR(ebi2_xmem); + goto err_disable_clk; + } + + /* Allegedly this turns the power save mode off */ + writel(0UL, ebi2_xmem + EBI2_XMEM_CFG); + + /* Disable all chipselects */ + val = readl(ebi2_base); + val &= ~EBI2_CSN_MASK; + writel(val, ebi2_base); + + /* Walk over the child nodes and see what chipselects we use */ + for_each_available_child_of_node(np, child) { + u32 csindex; + + /* Figure out the chipselect */ + ret = of_property_read_u32(child, "reg", &csindex); + if (ret) + return ret; + + if (csindex > 5) { + dev_err(dev, + "invalid chipselect %u, we only support 0-5\n", + csindex); + continue; + } + + qcom_ebi2_setup_chipselect(child, + dev, + ebi2_base, + ebi2_xmem, + csindex); + + /* We have at least one child */ + have_children = true; + } + + if (have_children) + return of_platform_default_populate(np, NULL, dev); + return 0; + +err_disable_clk: + clk_disable_unprepare(ebi2clk); +err_disable_2x_clk: + clk_disable_unprepare(ebi2xclk); + + return ret; +} + +static const struct of_device_id qcom_ebi2_of_match[] = { + { .compatible = "qcom,msm8660-ebi2", }, + { .compatible = "qcom,apq8060-ebi2", }, + { } +}; + +static struct platform_driver qcom_ebi2_driver = { + .probe = qcom_ebi2_probe, + .driver = { + .name = "qcom-ebi2", + .of_match_table = qcom_ebi2_of_match, + }, +}; +module_platform_driver(qcom_ebi2_driver); +MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); +MODULE_DESCRIPTION("Qualcomm EBI2 driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/bus/tegra-aconnect.c b/drivers/bus/tegra-aconnect.c index 7e4104b74fa8..084ae286fa23 100644 --- a/drivers/bus/tegra-aconnect.c +++ b/drivers/bus/tegra-aconnect.c @@ -15,24 +15,6 @@ #include <linux/pm_clock.h> #include <linux/pm_runtime.h> -static int tegra_aconnect_add_clock(struct device *dev, char *name) -{ - struct clk *clk; - int ret; - - clk = clk_get(dev, name); - if (IS_ERR(clk)) { - dev_err(dev, "%s clock not found\n", name); - return PTR_ERR(clk); - } - - ret = pm_clk_add_clk(dev, clk); - if (ret) - clk_put(clk); - - return ret; -} - static int tegra_aconnect_probe(struct platform_device *pdev) { int ret; @@ -44,11 +26,11 @@ static int tegra_aconnect_probe(struct platform_device *pdev) if (ret) return ret; - ret = tegra_aconnect_add_clock(&pdev->dev, "ape"); + ret = of_pm_clk_add_clk(&pdev->dev, "ape"); if (ret) goto clk_destroy; - ret = tegra_aconnect_add_clock(&pdev->dev, "apb2ape"); + ret = of_pm_clk_add_clk(&pdev->dev, "apb2ape"); if (ret) goto clk_destroy; diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c index fd129566c1ce..a6e5bee23385 100644 --- a/drivers/clk/mvebu/orion.c +++ b/drivers/clk/mvebu/orion.c @@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = { }; /* + * Orion 5181 + */ + +#define SAR_MV88F5181_TCLK_FREQ 8 +#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3 + +static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar) +{ + u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & + SAR_MV88F5181_TCLK_FREQ_MASK; + if (opt == 0) + return 133333333; + else if (opt == 1) + return 150000000; + else if (opt == 2) + return 166666667; + else + return 0; +} + +#define SAR_MV88F5181_CPU_FREQ 4 +#define SAR_MV88F5181_CPU_FREQ_MASK 0xf + +static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar) +{ + u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & + SAR_MV88F5181_CPU_FREQ_MASK; + if (opt == 0) + return 333333333; + else if (opt == 1 || opt == 2) + return 400000000; + else if (opt == 3) + return 500000000; + else + return 0; +} + +static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id, + int *mult, int *div) +{ + u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & + SAR_MV88F5181_CPU_FREQ_MASK; + if (opt == 0 || opt == 1) { + *mult = 1; + *div = 2; + } else if (opt == 2 || opt == 3) { + *mult = 1; + *div = 3; + } else { + *mult = 0; + *div = 1; + } +} + +static const struct coreclk_soc_desc mv88f5181_coreclks = { + .get_tclk_freq = mv88f5181_get_tclk_freq, + .get_cpu_freq = mv88f5181_get_cpu_freq, + .get_clk_ratio = mv88f5181_get_clk_ratio, + .ratios = orion_coreclk_ratios, + .num_ratios = ARRAY_SIZE(orion_coreclk_ratios), +}; + +static void __init mv88f5181_clk_init(struct device_node *np) +{ + return mvebu_coreclk_setup(np, &mv88f5181_coreclks); +} + +CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init); + +/* * Orion 5182 */ diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 8a753fd5b79d..245190839359 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -361,7 +361,7 @@ config CLKSRC_METAG_GENERIC config CLKSRC_EXYNOS_MCT bool "Exynos multi core timer driver" if COMPILE_TEST - depends on ARM + depends on ARM || ARM64 help Support for Multi Core Timer controller on Exynos SoCs. diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 41840d02c331..8f3488b80896 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -223,6 +223,7 @@ static u64 notrace exynos4_read_sched_clock(void) return exynos4_read_count_32(); } +#if defined(CONFIG_ARM) static struct delay_timer exynos4_delay_timer; static cycles_t exynos4_read_current_timer(void) @@ -231,14 +232,17 @@ static cycles_t exynos4_read_current_timer(void) "cycles_t needs to move to 32-bit for ARM64 usage"); return exynos4_read_count_32(); } +#endif static int __init exynos4_clocksource_init(void) { exynos4_mct_frc_start(); +#if defined(CONFIG_ARM) exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; exynos4_delay_timer.freq = clk_rate; register_current_timer_delay(&exynos4_delay_timer); +#endif if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 0e22f241403b..bca172d42c74 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -209,5 +209,6 @@ config HAVE_ARM_SMCCC source "drivers/firmware/broadcom/Kconfig" source "drivers/firmware/google/Kconfig" source "drivers/firmware/efi/Kconfig" +source "drivers/firmware/meson/Kconfig" endmenu diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 44a59dcfc398..898ac41fa8b3 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a obj-y += broadcom/ +obj-y += meson/ obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ obj-$(CONFIG_EFI) += efi/ obj-$(CONFIG_UEFI_CPER) += efi/ diff --git a/drivers/firmware/meson/Kconfig b/drivers/firmware/meson/Kconfig new file mode 100644 index 000000000000..170d7e8bcdfb --- /dev/null +++ b/drivers/firmware/meson/Kconfig @@ -0,0 +1,9 @@ +# +# Amlogic Secure Monitor driver +# +config MESON_SM + bool + default ARCH_MESON + depends on ARM64_4K_PAGES + help + Say y here to enable the Amlogic secure monitor driver diff --git a/drivers/firmware/meson/Makefile b/drivers/firmware/meson/Makefile new file mode 100644 index 000000000000..9ab3884f96bc --- /dev/null +++ b/drivers/firmware/meson/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MESON_SM) += meson_sm.o diff --git a/drivers/firmware/meson/meson_sm.c b/drivers/firmware/meson/meson_sm.c new file mode 100644 index 000000000000..b0d254930ed3 --- /dev/null +++ b/drivers/firmware/meson/meson_sm.c @@ -0,0 +1,248 @@ +/* + * Amlogic Secure Monitor driver + * + * Copyright (C) 2016 Endless Mobile, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#define pr_fmt(fmt) "meson-sm: " fmt + +#include <linux/arm-smccc.h> +#include <linux/bug.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/printk.h> +#include <linux/types.h> +#include <linux/sizes.h> + +#include <linux/firmware/meson/meson_sm.h> + +struct meson_sm_cmd { + unsigned int index; + u32 smc_id; +}; +#define CMD(d, s) { .index = (d), .smc_id = (s), } + +struct meson_sm_chip { + unsigned int shmem_size; + u32 cmd_shmem_in_base; + u32 cmd_shmem_out_base; + struct meson_sm_cmd cmd[]; +}; + +struct meson_sm_chip gxbb_chip = { + .shmem_size = SZ_4K, + .cmd_shmem_in_base = 0x82000020, + .cmd_shmem_out_base = 0x82000021, + .cmd = { + CMD(SM_EFUSE_READ, 0x82000030), + CMD(SM_EFUSE_WRITE, 0x82000031), + CMD(SM_EFUSE_USER_MAX, 0x82000033), + { /* sentinel */ }, + }, +}; + +struct meson_sm_firmware { + const struct meson_sm_chip *chip; + void __iomem *sm_shmem_in_base; + void __iomem *sm_shmem_out_base; +}; + +static struct meson_sm_firmware fw; + +static u32 meson_sm_get_cmd(const struct meson_sm_chip *chip, + unsigned int cmd_index) +{ + const struct meson_sm_cmd *cmd = chip->cmd; + + while (cmd->smc_id && cmd->index != cmd_index) + cmd++; + + return cmd->smc_id; +} + +static u32 __meson_sm_call(u32 cmd, u32 arg0, u32 arg1, u32 arg2, + u32 arg3, u32 arg4) +{ + struct arm_smccc_res res; + + arm_smccc_smc(cmd, arg0, arg1, arg2, arg3, arg4, 0, 0, &res); + return res.a0; +} + +static void __iomem *meson_sm_map_shmem(u32 cmd_shmem, unsigned int size) +{ + u32 sm_phy_base; + + sm_phy_base = __meson_sm_call(cmd_shmem, 0, 0, 0, 0, 0); + if (!sm_phy_base) + return 0; + + return ioremap_cache(sm_phy_base, size); +} + +/** + * meson_sm_call - generic SMC32 call to the secure-monitor + * + * @cmd_index: Index of the SMC32 function ID + * @ret: Returned value + * @arg0: SMC32 Argument 0 + * @arg1: SMC32 Argument 1 + * @arg2: SMC32 Argument 2 + * @arg3: SMC32 Argument 3 + * @arg4: SMC32 Argument 4 + * + * Return: 0 on success, a negative value on error + */ +int meson_sm_call(unsigned int cmd_index, u32 *ret, u32 arg0, + u32 arg1, u32 arg2, u32 arg3, u32 arg4) +{ + u32 cmd, lret; + + if (!fw.chip) + return -ENOENT; + + cmd = meson_sm_get_cmd(fw.chip, cmd_index); + if (!cmd) + return -EINVAL; + + lret = __meson_sm_call(cmd, arg0, arg1, arg2, arg3, arg4); + + if (ret) + *ret = lret; + + return 0; +} +EXPORT_SYMBOL(meson_sm_call); + +/** + * meson_sm_call_read - retrieve data from secure-monitor + * + * @buffer: Buffer to store the retrieved data + * @cmd_index: Index of the SMC32 function ID + * @arg0: SMC32 Argument 0 + * @arg1: SMC32 Argument 1 + * @arg2: SMC32 Argument 2 + * @arg3: SMC32 Argument 3 + * @arg4: SMC32 Argument 4 + * + * Return: size of read data on success, a negative value on error + */ +int meson_sm_call_read(void *buffer, unsigned int cmd_index, u32 arg0, + u32 arg1, u32 arg2, u32 arg3, u32 arg4) +{ + u32 size; + + if (!fw.chip) + return -ENOENT; + + if (!fw.chip->cmd_shmem_out_base) + return -EINVAL; + + if (meson_sm_call(cmd_index, &size, arg0, arg1, arg2, arg3, arg4) < 0) + return -EINVAL; + + if (!size || size > fw.chip->shmem_size) + return -EINVAL; + + if (buffer) + memcpy(buffer, fw.sm_shmem_out_base, size); + + return size; +} +EXPORT_SYMBOL(meson_sm_call_read); + +/** + * meson_sm_call_write - send data to secure-monitor + * + * @buffer: Buffer containing data to send + * @size: Size of the data to send + * @cmd_index: Index of the SMC32 function ID + * @arg0: SMC32 Argument 0 + * @arg1: SMC32 Argument 1 + * @arg2: SMC32 Argument 2 + * @arg3: SMC32 Argument 3 + * @arg4: SMC32 Argument 4 + * + * Return: size of sent data on success, a negative value on error + */ +int meson_sm_call_write(void *buffer, unsigned int size, unsigned int cmd_index, + u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4) +{ + u32 written; + + if (!fw.chip) + return -ENOENT; + |