diff options
Diffstat (limited to 'drivers')
56 files changed, 10240 insertions, 496 deletions
diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c index 076297592754..5917b4b5fb99 100644 --- a/drivers/base/pinctrl.c +++ b/drivers/base/pinctrl.c @@ -91,9 +91,13 @@ cleanup_alloc: devm_kfree(dev, dev->pins); dev->pins = NULL; - /* Only return deferrals */ - if (ret != -EPROBE_DEFER) - ret = 0; + /* Return deferrals */ + if (ret == -EPROBE_DEFER) + return ret; + /* Return serious errors */ + if (ret == -EINVAL) + return ret; + /* We ignore errors like -ENOENT meaning no pinctrl state */ - return ret; + return 0; } diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 1b342a3842c8..e38989a4fa0c 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -458,6 +458,11 @@ static int mxc_gpio_probe(struct platform_device *pdev) if (err) goto out_bgio; + if (of_property_read_bool(np, "gpio-ranges")) { + port->gc.request = gpiochip_generic_request; + port->gc.free = gpiochip_generic_free; + } + port->gc.to_irq = mxc_gpio_to_irq; port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : pdev->id * 32; @@ -510,7 +515,7 @@ static int __init gpio_mxc_init(void) { return platform_driver_register(&mxc_gpio_driver); } -postcore_initcall(gpio_mxc_init); +subsys_initcall(gpio_mxc_init); MODULE_AUTHOR("Freescale Semiconductor, " "Daniel Mack <danielncaiaq.de>, " diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 53ff25ac66d8..23be4daefeed 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -71,6 +71,8 @@ LIST_HEAD(gpio_devices); static void gpiochip_free_hogs(struct gpio_chip *chip); static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip); +static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip); +static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip); static bool gpiolib_initialized; @@ -1167,6 +1169,10 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data) if (status) goto err_remove_from_list; + status = gpiochip_irqchip_init_valid_mask(chip); + if (status) + goto err_remove_from_list; + status = of_gpiochip_add(chip); if (status) goto err_remove_chip; @@ -1192,6 +1198,7 @@ err_remove_chip: acpi_gpiochip_remove(chip); gpiochip_free_hogs(chip); of_gpiochip_remove(chip); + gpiochip_irqchip_free_valid_mask(chip); err_remove_from_list: spin_lock_irqsave(&gpio_lock, flags); list_del(&gdev->list); @@ -1401,6 +1408,40 @@ static struct gpio_chip *find_chip_by_name(const char *name) * The following is irqchip helper code for gpiochips. */ +static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip) +{ + int i; + + if (!gpiochip->irq_need_valid_mask) + return 0; + + gpiochip->irq_valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio), + sizeof(long), GFP_KERNEL); + if (!gpiochip->irq_valid_mask) + return -ENOMEM; + + /* Assume by default all GPIOs are valid */ + for (i = 0; i < gpiochip->ngpio; i++) + set_bit(i, gpiochip->irq_valid_mask); + + return 0; +} + +static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip) +{ + kfree(gpiochip->irq_valid_mask); + gpiochip->irq_valid_mask = NULL; +} + +static bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip, + unsigned int offset) +{ + /* No mask means all valid */ + if (likely(!gpiochip->irq_valid_mask)) + return true; + return test_bit(offset, gpiochip->irq_valid_mask); +} + /** * gpiochip_set_chained_irqchip() - sets a chained irqchip to a gpiochip * @gpiochip: the gpiochip to set the irqchip chain to @@ -1442,9 +1483,12 @@ void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip, } /* Set the parent IRQ for all affected IRQs */ - for (offset = 0; offset < gpiochip->ngpio; offset++) + for (offset = 0; offset < gpiochip->ngpio; offset++) { + if (!gpiochip_irqchip_irq_valid(gpiochip, offset)) + continue; irq_set_parent(irq_find_mapping(gpiochip->irqdomain, offset), parent_irq); + } } EXPORT_SYMBOL_GPL(gpiochip_set_chained_irqchip); @@ -1551,9 +1595,12 @@ static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) /* Remove all IRQ mappings and delete the domain */ if (gpiochip->irqdomain) { - for (offset = 0; offset < gpiochip->ngpio; offset++) + for (offset = 0; offset < gpiochip->ngpio; offset++) { + if (!gpiochip_irqchip_irq_valid(gpiochip, offset)) + continue; irq_dispose_mapping( irq_find_mapping(gpiochip->irqdomain, offset)); + } irq_domain_remove(gpiochip->irqdomain); } @@ -1562,6 +1609,8 @@ static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) gpiochip->irqchip->irq_release_resources = NULL; gpiochip->irqchip = NULL; } + + gpiochip_irqchip_free_valid_mask(gpiochip); } /** @@ -1597,6 +1646,7 @@ int _gpiochip_irqchip_add(struct gpio_chip *gpiochip, struct lock_class_key *lock_key) { struct device_node *of_node; + bool irq_base_set = false; unsigned int offset; unsigned irq_base = 0; @@ -1646,13 +1696,17 @@ int _gpiochip_irqchip_add(struct gpio_chip *gpiochip, * necessary to allocate descriptors for all IRQs. */ for (offset = 0; offset < gpiochip->ngpio; offset++) { + if (!gpiochip_irqchip_irq_valid(gpiochip, offset)) + continue; irq_base = irq_create_mapping(gpiochip->irqdomain, offset); - if (offset == 0) + if (!irq_base_set) { /* * Store the base into the gpiochip to be used when * unmapping the irqs. */ gpiochip->irq_base = irq_base; + irq_base_set = true; + } } acpi_gpiochip_request_interrupts(gpiochip); @@ -1664,6 +1718,12 @@ EXPORT_SYMBOL_GPL(_gpiochip_irqchip_add); #else /* CONFIG_GPIOLIB_IRQCHIP */ static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) {} +static inline int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip) +{ + return 0; +} +static inline void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip) +{ } #endif /* CONFIG_GPIOLIB_IRQCHIP */ diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b3fe1d339632..0e75d94972ba 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -254,6 +254,7 @@ config PINCTRL_ZYNQ help This selects the pinctrl driver for Xilinx Zynq. +source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/freescale/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8ebd7b8e1621..11bad373dfe0 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o +obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-y += bcm/ obj-$(CONFIG_PINCTRL_BERLIN) += berlin/ obj-y += freescale/ diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig new file mode 100644 index 000000000000..998eabef3a65 --- /dev/null +++ b/drivers/pinctrl/aspeed/Kconfig @@ -0,0 +1,24 @@ +config PINCTRL_ASPEED + bool + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + depends on MFD_SYSCON + select PINMUX + select PINCONF + select GENERIC_PINCONF + select REGMAP_MMIO + +config PINCTRL_ASPEED_G4 + bool "Aspeed G4 SoC pin control" + depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 4th + generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G5 + bool "Aspeed G5 SoC pin control" + depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 5th + generation SoCs. GPIO is provided by a separate GPIO driver. diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile new file mode 100644 index 000000000000..191ed0fc1804 --- /dev/null +++ b/drivers/pinctrl/aspeed/Makefile @@ -0,0 +1,6 @@ +# Aspeed pinctrl support + +ccflags-y += -Woverride-init +obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o +obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o +obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c new file mode 100644 index 000000000000..a21b071ff290 --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -0,0 +1,1231 @@ +/* + * Copyright (C) 2016 IBM Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/bitops.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/string.h> +#include <linux/types.h> + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-aspeed.h" + +/* + * Uses undefined macros for symbol naming and references, eg GPIOA0, MAC1LINK, + * TIMER3 etc. + * + * Pins are defined in GPIO bank order: + * + * GPIOA0: 0 + * ... + * GPIOA7: 7 + * GPIOB0: 8 + * ... + * GPIOZ7: 207 + * GPIOAA0: 208 + * ... + * GPIOAB3: 219 + * + * Not all pins have their signals defined (yet). + */ + +#define A4 2 +SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); + +#define I2C9_DESC SIG_DESC_SET(SCU90, 22) + +#define C5 4 +SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4)); +MS_PIN_DECL(C5, GPIOA4, SCL9, TIMER5); + +FUNC_GROUP_DECL(TIMER5, C5); + +#define B4 5 +SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5)); +MS_PIN_DECL(B4, GPIOA5, SDA9, TIMER6); + +FUNC_GROUP_DECL(TIMER6, B4); +FUNC_GROUP_DECL(I2C9, C5, B4); + +#define MDIO2_DESC SIG_DESC_SET(SCU90, 2) + +#define A3 6 +SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6)); +MS_PIN_DECL(A3, GPIOA6, MDC2, TIMER7); + +FUNC_GROUP_DECL(TIMER7, A3); + +#define D5 7 +SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7)); +MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8); + +FUNC_GROUP_DECL(TIMER8, D5); +FUNC_GROUP_DECL(MDIO2, A3, D5); + +#define H19 13 +#define H19_DESC SIG_DESC_SET(SCU80, 13) +SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H19_DESC); +MS_PIN_DECL(H19, GPIOB5, LPCPD, LPCSMI); + +FUNC_GROUP_DECL(LPCPD, H19); +FUNC_GROUP_DECL(LPCSMI, H19); + +#define H20 14 +SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); + +#define SD1_DESC SIG_DESC_SET(SCU90, 0) +#define I2C10_DESC SIG_DESC_SET(SCU90, 23) + +#define C4 16 +SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); +MS_PIN_DECL(C4, GPIOC0, SD1CLK, SCL10); + +#define B3 17 +SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); +MS_PIN_DECL(B3, GPIOC1, SD1CMD, SDA10); + +FUNC_GROUP_DECL(I2C10, C4, B3); + +#define I2C11_DESC SIG_DESC_SET(SCU90, 24) + +#define A2 18 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); +MS_PIN_DECL(A2, GPIOC2, SD1DAT0, SCL11); + +#define E5 19 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); +MS_PIN_DECL(E5, GPIOC3, SD1DAT1, SDA11); + +FUNC_GROUP_DECL(I2C11, A2, E5); + +#define I2C12_DESC SIG_DESC_SET(SCU90, 25) + +#define D4 20 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); +MS_PIN_DECL(D4, GPIOC4, SD1DAT2, SCL12); + +#define C3 21 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); +MS_PIN_DECL(C3, GPIOC5, SD1DAT3, SDA12); + +FUNC_GROUP_DECL(I2C12, D4, C3); + +#define I2C13_DESC SIG_DESC_SET(SCU90, 26) + +#define B2 22 +SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); +MS_PIN_DECL(B2, GPIOC6, SD1CD, SCL13); + +#define A1 23 +SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); +MS_PIN_DECL(A1, GPIOC7, SD1WP, SDA13); + +FUNC_GROUP_DECL(I2C13, B2, A1); +FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1); + +#define SD2_DESC SIG_DESC_SET(SCU90, 1) +#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) +#define GPID0_DESC SIG_DESC_SET(SCU8C, 8) + +#define A18 24 +SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); +SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); +MS_PIN_DECL(A18, GPIOD0, SD2CLK, GPID0IN); + +#define D16 25 +SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); +SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); +MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT); + +FUNC_GROUP_DECL(GPID0, A18, D16); + +#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) +#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) +#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) +#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) +#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) + +#define D15 32 +SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); +SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); +MS_PIN_DECL(D15, GPIOE0, NCTS3, GPIE0IN); + +FUNC_GROUP_DECL(NCTS3, D15); + +#define C15 33 +SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); +SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); +MS_PIN_DECL(C15, GPIOE1, NDCD3, GPIE0OUT); + +FUNC_GROUP_DECL(NDCD3, C15); +FUNC_GROUP_DECL(GPIE0, D15, C15); + +#define B15 34 +SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); +SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); +MS_PIN_DECL(B15, GPIOE2, NDSR3, GPIE2IN); + +FUNC_GROUP_DECL(NDSR3, B15); + +#define A15 35 +SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); +SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); +MS_PIN_DECL(A15, GPIOE3, NRI3, GPIE2OUT); + +FUNC_GROUP_DECL(NRI3, A15); +FUNC_GROUP_DECL(GPIE2, B15, A15); + +#define E14 36 +SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); +SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); +MS_PIN_DECL(E14, GPIOE4, NDTR3, GPIE4IN); + +FUNC_GROUP_DECL(NDTR3, E14); + +#define D14 37 +SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); +SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); +MS_PIN_DECL(D14, GPIOE5, NRTS3, GPIE4OUT); + +FUNC_GROUP_DECL(NRTS3, D14); +FUNC_GROUP_DECL(GPIE4, E14, D14); + +#define C14 38 +SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); +SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); +MS_PIN_DECL(C14, GPIOE6, TXD3, GPIE6IN); + +FUNC_GROUP_DECL(TXD3, C14); + +#define B14 39 +SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); +SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); +MS_PIN_DECL(B14, GPIOE7, RXD3, GPIE6OUT); + +FUNC_GROUP_DECL(RXD3, B14); +FUNC_GROUP_DECL(GPIE6, C14, B14); + +#define D18 40 +SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24)); + +#define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0) + +#define B19 41 +SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); +SIG_EXPR_DECL(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12)); +SIG_EXPR_DECL(SIOPBI, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); +MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI); +FUNC_GROUP_DECL(NDCD4, B19); +FUNC_GROUP_DECL(SIOPBI, B19); + +#define D17 43 +SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); +SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); +SIG_EXPR_DECL(SIOPBO, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); +MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO); +FUNC_GROUP_DECL(NRI4, D17); +FUNC_GROUP_DECL(SIOPBO, D17); + +FUNC_GROUP_DECL(ACPI, B19, D17); + +#define E16 46 +SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30)); + +#define C17 47 +SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31)); + +#define AA22 54 +SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6)); + +#define U18 55 +SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7)); + +#define UART6_DESC SIG_DESC_SET(SCU90, 7) +#define ROM16_DESC SIG_DESC_SET(SCU90, 6) +#define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4) +#define BOOT_SRC_NOR { HW_STRAP1, GENMASK(1, 0), 0, 0 } + +#define A8 56 +SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD8, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, UART6_DESC); +MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); + +#define C7 57 +SIG_EXPR_DECL(ROMD9, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD9, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NDCD6, NDCD6, UART6_DESC); +MS_PIN_DECL(C7, GPIOH1, ROMD9, NDCD6); + +#define B7 58 +SIG_EXPR_DECL(ROMD10, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD10, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NDSR6, NDSR6, UART6_DESC); +MS_PIN_DECL(B7, GPIOH2, ROMD10, NDSR6); + +#define A7 59 +SIG_EXPR_DECL(ROMD11, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD11, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NRI6, NRI6, UART6_DESC); +MS_PIN_DECL(A7, GPIOH3, ROMD11, NRI6); + +#define D7 60 +SIG_EXPR_DECL(ROMD12, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD12, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NDTR6, NDTR6, UART6_DESC); +MS_PIN_DECL(D7, GPIOH4, ROMD12, NDTR6); + +#define B6 61 +SIG_EXPR_DECL(ROMD13, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD13, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NRTS6, NRTS6, UART6_DESC); +MS_PIN_DECL(B6, GPIOH5, ROMD13, NRTS6); + +#define A6 62 +SIG_EXPR_DECL(ROMD14, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD14, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(TXD6, TXD6, UART6_DESC); +MS_PIN_DECL(A6, GPIOH6, ROMD14, TXD6); + +#define E7 63 +SIG_EXPR_DECL(ROMD15, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD15, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(RXD6, RXD6, UART6_DESC); +MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6); + +FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); + +#define J3 75 +SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11)); + +#define T4 76 +SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12)); + +#define U2 77 +SSSF_PIN_DECL(U2, GPIOJ5, VGAVS, SIG_DESC_SET(SCU84, 13)); + +#define T2 78 +SSSF_PIN_DECL(T2, GPIOJ6, DDCCLK, SIG_DESC_SET(SCU84, 14)); + +#define T1 79 +SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15)); + +#define I2C5_DESC SIG_DESC_SET(SCU90, 18) + +#define E3 80 +SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); +SS_PIN_DECL(E3, GPIOK0, SCL5); + +#define D2 81 +SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); +SS_PIN_DECL(D2, GPIOK1, SDA5); + +FUNC_GROUP_DECL(I2C5, E3, D2); +< |