diff options
Diffstat (limited to 'include/linux/mfd')
| -rw-r--r-- | include/linux/mfd/axp20x.h | 5 | ||||
| -rw-r--r-- | include/linux/mfd/cros_ec.h | 4 | ||||
| -rw-r--r-- | include/linux/mfd/cros_ec_commands.h | 17 | ||||
| -rw-r--r-- | include/linux/mfd/rave-sp.h | 60 | ||||
| -rw-r--r-- | include/linux/mfd/rtsx_common.h | 50 | ||||
| -rw-r--r-- | include/linux/mfd/rtsx_pci.h | 1141 | ||||
| -rw-r--r-- | include/linux/mfd/rtsx_usb.h | 628 |
7 files changed, 81 insertions, 1824 deletions
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index 78dc85365c4f..080798f17ece 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -645,11 +645,6 @@ struct axp20x_dev { const struct regmap_irq_chip *regmap_irq_chip; }; -struct axp288_extcon_pdata { - /* GPIO pin control to switch D+/D- lines b/w PMIC and SOC */ - struct gpio_desc *gpio_mux_cntl; -}; - /* generic helper function for reading 9-16 bit wide regs */ static inline int axp20x_read_variable_width(struct regmap *regmap, unsigned int reg, unsigned int width) diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h index 4e887ba22635..c61535979b8f 100644 --- a/include/linux/mfd/cros_ec.h +++ b/include/linux/mfd/cros_ec.h @@ -322,6 +322,10 @@ extern struct attribute_group cros_ec_attr_group; extern struct attribute_group cros_ec_lightbar_attr_group; extern struct attribute_group cros_ec_vbc_attr_group; +/* debugfs stuff */ +int cros_ec_debugfs_init(struct cros_ec_dev *ec); +void cros_ec_debugfs_remove(struct cros_ec_dev *ec); + /* ACPI GPE handler */ #ifdef CONFIG_ACPI diff --git a/include/linux/mfd/cros_ec_commands.h b/include/linux/mfd/cros_ec_commands.h index 2b16e95b9bb8..a83f6498b95e 100644 --- a/include/linux/mfd/cros_ec_commands.h +++ b/include/linux/mfd/cros_ec_commands.h @@ -2904,16 +2904,33 @@ enum usb_pd_control_mux { USB_PD_CTRL_MUX_AUTO = 5, }; +enum usb_pd_control_swap { + USB_PD_CTRL_SWAP_NONE = 0, + USB_PD_CTRL_SWAP_DATA = 1, + USB_PD_CTRL_SWAP_POWER = 2, + USB_PD_CTRL_SWAP_VCONN = 3, + USB_PD_CTRL_SWAP_COUNT +}; + struct ec_params_usb_pd_control { uint8_t port; uint8_t role; uint8_t mux; + uint8_t swap; } __packed; #define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ #define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ #define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */ +#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ +#define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6) /* Partner externally powerd */ + struct ec_response_usb_pd_control_v1 { uint8_t enabled; uint8_t role; diff --git a/include/linux/mfd/rave-sp.h b/include/linux/mfd/rave-sp.h new file mode 100644 index 000000000000..796fb9794c9e --- /dev/null +++ b/include/linux/mfd/rave-sp.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* + * Core definitions for RAVE SP MFD driver. + * + * Copyright (C) 2017 Zodiac Inflight Innovations + */ + +#ifndef _LINUX_RAVE_SP_H_ +#define _LINUX_RAVE_SP_H_ + +#include <linux/notifier.h> + +enum rave_sp_command { + RAVE_SP_CMD_GET_FIRMWARE_VERSION = 0x20, + RAVE_SP_CMD_GET_BOOTLOADER_VERSION = 0x21, + RAVE_SP_CMD_BOOT_SOURCE = 0x26, + RAVE_SP_CMD_GET_BOARD_COPPER_REV = 0x2B, + RAVE_SP_CMD_GET_GPIO_STATE = 0x2F, + + RAVE_SP_CMD_STATUS = 0xA0, + RAVE_SP_CMD_SW_WDT = 0xA1, + RAVE_SP_CMD_PET_WDT = 0xA2, + RAVE_SP_CMD_RESET = 0xA7, + RAVE_SP_CMD_RESET_REASON = 0xA8, + + RAVE_SP_CMD_REQ_COPPER_REV = 0xB6, + RAVE_SP_CMD_GET_I2C_DEVICE_STATUS = 0xBA, + RAVE_SP_CMD_GET_SP_SILICON_REV = 0xB9, + RAVE_SP_CMD_CONTROL_EVENTS = 0xBB, + + RAVE_SP_EVNT_BASE = 0xE0, +}; + +struct rave_sp; + +static inline unsigned long rave_sp_action_pack(u8 event, u8 value) +{ + return ((unsigned long)value << 8) | event; +} + +static inline u8 rave_sp_action_unpack_event(unsigned long action) +{ + return action; +} + +static inline u8 rave_sp_action_unpack_value(unsigned long action) +{ + return action >> 8; +} + +int rave_sp_exec(struct rave_sp *sp, + void *__data, size_t data_size, + void *reply_data, size_t reply_data_size); + +struct device; +int devm_rave_sp_register_event_notifier(struct device *dev, + struct notifier_block *nb); + +#endif /* _LINUX_RAVE_SP_H_ */ diff --git a/include/linux/mfd/rtsx_common.h b/include/linux/mfd/rtsx_common.h deleted file mode 100644 index 443176ee1ab0..000000000000 --- a/include/linux/mfd/rtsx_common.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Driver for Realtek driver-based card reader - * - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2, or (at your option) any - * later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - * - * Author: - * Wei WANG <wei_wang@realsil.com.cn> - */ - -#ifndef __RTSX_COMMON_H -#define __RTSX_COMMON_H - -#define DRV_NAME_RTSX_PCI "rtsx_pci" -#define DRV_NAME_RTSX_PCI_SDMMC "rtsx_pci_sdmmc" -#define DRV_NAME_RTSX_PCI_MS "rtsx_pci_ms" - -#define RTSX_REG_PAIR(addr, val) (((u32)(addr) << 16) | (u8)(val)) - -#define RTSX_SSC_DEPTH_4M 0x01 -#define RTSX_SSC_DEPTH_2M 0x02 -#define RTSX_SSC_DEPTH_1M 0x03 -#define RTSX_SSC_DEPTH_500K 0x04 -#define RTSX_SSC_DEPTH_250K 0x05 - -#define RTSX_SD_CARD 0 -#define RTSX_MS_CARD 1 - -#define CLK_TO_DIV_N 0 -#define DIV_N_TO_CLK 1 - -struct platform_device; - -struct rtsx_slot { - struct platform_device *p_dev; - void (*card_event)(struct platform_device *p_dev); -}; - -#endif diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h deleted file mode 100644 index a2a1318a3d0c..000000000000 --- a/include/linux/mfd/rtsx_pci.h +++ /dev/null @@ -1,1141 +0,0 @@ -/* Driver for Realtek PCI-Express card reader - * - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2, or (at your option) any - * later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - * - * Author: - * Wei WANG <wei_wang@realsil.com.cn> - */ - -#ifndef __RTSX_PCI_H -#define __RTSX_PCI_H - -#include <linux/sched.h> -#include <linux/pci.h> -#include <linux/mfd/rtsx_common.h> - -#define MAX_RW_REG_CNT 1024 - -#define RTSX_HCBAR 0x00 -#define RTSX_HCBCTLR 0x04 -#define STOP_CMD (0x01 << 28) -#define READ_REG_CMD 0 -#define WRITE_REG_CMD 1 -#define CHECK_REG_CMD 2 - -#define RTSX_HDBAR 0x08 -#define SG_INT 0x04 -#define SG_END 0x02 -#define SG_VALID 0x01 -#define SG_NO_OP 0x00 -#define SG_TRANS_DATA (0x02 << 4) -#define SG_LINK_DESC (0x03 << 4) -#define RTSX_HDBCTLR 0x0C -#define SDMA_MODE 0x00 -#define ADMA_MODE (0x02 << 26) -#define STOP_DMA (0x01 << 28) -#define TRIG_DMA (0x01 << 31) - -#define RTSX_HAIMR 0x10 -#define HAIMR_TRANS_START (0x01 << 31) -#define HAIMR_READ 0x00 -#define HAIMR_WRITE (0x01 << 30) -#define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ) -#define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE) -#define HAIMR_TRANS_END (HAIMR_TRANS_START) - -#define RTSX_BIPR 0x14 -#define CMD_DONE_INT (1 << 31) -#define DATA_DONE_INT (1 << 30) -#define TRANS_OK_INT (1 << 29) -#define TRANS_FAIL_INT (1 << 28) -#define XD_INT (1 << 27) -#define MS_INT (1 << 26) -#define SD_INT (1 << 25) -#define GPIO0_INT (1 << 24) -#define OC_INT (1 << 23) -#define SD_WRITE_PROTECT (1 << 19) -#define XD_EXIST (1 << 18) -#define MS_EXIST (1 << 17) -#define SD_EXIST (1 << 16) -#define DELINK_INT GPIO0_INT -#define MS_OC_INT (1 << 23) -#define SD_OC_INT (1 << 22) - -#define CARD_INT (XD_INT | MS_INT | SD_INT) -#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) -#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \ - CARD_INT | GPIO0_INT | OC_INT) -#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) - -#define RTSX_BIER 0x18 -#define CMD_DONE_INT_EN (1 << 31) -#define DATA_DONE_INT_EN (1 << 30) -#define TRANS_OK_INT_EN (1 << 29) -#define TRANS_FAIL_INT_EN (1 << 28) -#define XD_INT_EN (1 << 27) -#define MS_INT_EN (1 << 26) -#define SD_INT_EN (1 << 25) -#define GPIO0_INT_EN (1 << 24) -#define OC_INT_EN (1 << 23) -#define DELINK_INT_EN GPIO0_INT_EN -#define MS_OC_INT_EN (1 << 23) -#define SD_OC_INT_EN (1 << 22) - - -/* - * macros for easy use - */ -#define rtsx_pci_writel(pcr, reg, value) \ - iowrite32(value, (pcr)->remap_addr + reg) -#define rtsx_pci_readl(pcr, reg) \ - ioread32((pcr)->remap_addr + reg) -#define rtsx_pci_writew(pcr, reg, value) \ - iowrite16(value, (pcr)->remap_addr + reg) -#define rtsx_pci_readw(pcr, reg) \ - ioread16((pcr)->remap_addr + reg) -#define rtsx_pci_writeb(pcr, reg, value) \ - iowrite8(value, (pcr)->remap_addr + reg) -#define rtsx_pci_readb(pcr, reg) \ - ioread8((pcr)->remap_addr + reg) - -#define rtsx_pci_read_config_byte(pcr, where, val) \ - pci_read_config_byte((pcr)->pci, where, val) - -#define rtsx_pci_write_config_byte(pcr, where, val) \ - pci_write_config_byte((pcr)->pci, where, val) - -#define rtsx_pci_read_config_dword(pcr, where, val) \ - pci_read_config_dword((pcr)->pci, where, val) - -#define rtsx_pci_write_config_dword(pcr, where, val) \ - pci_write_config_dword((pcr)->pci, where, val) - -#define STATE_TRANS_NONE 0 -#define STATE_TRANS_CMD 1 -#define STATE_TRANS_BUF 2 -#define STATE_TRANS_SG 3 - -#define TRANS_NOT_READY 0 -#define TRANS_RESULT_OK 1 -#define TRANS_RESULT_FAIL 2 -#define TRANS_NO_DEVICE 3 - -#define RTSX_RESV_BUF_LEN 4096 -#define HOST_CMDS_BUF_LEN 1024 -#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN) -#define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8) -#define MAX_SG_ITEM_LEN 0x80000 -#define HOST_TO_DEVICE 0 -#define DEVICE_TO_HOST 1 - -#define OUTPUT_3V3 0 -#define OUTPUT_1V8 1 - -#define RTSX_PHASE_MAX 32 -#define RX_TUNING_CNT 3 - -#define MS_CFG 0xFD40 -#define SAMPLE_TIME_RISING 0x00 -#define SAMPLE_TIME_FALLING 0x80 -#define PUSH_TIME_DEFAULT 0x00 -#define PUSH_TIME_ODD 0x40 -#define NO_EXTEND_TOGGLE 0x00 -#define EXTEND_TOGGLE_CHK 0x20 -#define MS_BUS_WIDTH_1 0x00 -#define MS_BUS_WIDTH_4 0x10 -#define MS_BUS_WIDTH_8 0x18 -#define MS_2K_SECTOR_MODE 0x04 -#define MS_512_SECTOR_MODE 0x00 -#define MS_TOGGLE_TIMEOUT_EN 0x00 -#define MS_TOGGLE_TIMEOUT_DISEN 0x01 -#define MS_NO_CHECK_INT 0x02 -#define MS_TPC 0xFD41 -#define MS_TRANS_CFG 0xFD42 -#define WAIT_INT 0x80 -#define NO_WAIT_INT 0x00 -#define NO_AUTO_READ_INT_REG 0x00 -#define AUTO_READ_INT_REG 0x40 -#define MS_CRC16_ERR 0x20 -#define MS_RDY_TIMEOUT 0x10 -#define MS_INT_CMDNK 0x08 -#define MS_INT_BREQ 0x04 -#define MS_INT_ERR 0x02 -#define MS_INT_CED 0x01 -#define MS_TRANSFER 0xFD43 -#define MS_TRANSFER_START 0x80 -#define MS_TRANSFER_END 0x40 -#define MS_TRANSFER_ERR 0x20 -#define MS_BS_STATE 0x10 -#define MS_TM_READ_BYTES 0x00 -#define MS_TM_NORMAL_READ 0x01 -#define MS_TM_WRITE_BYTES 0x04 -#define MS_TM_NORMAL_WRITE 0x05 -#define MS_TM_AUTO_READ 0x08 -#define MS_TM_AUTO_WRITE 0x0C -#define MS_INT_REG 0xFD44 -#define MS_BYTE_CNT 0xFD45 -#define MS_SECTOR_CNT_L 0xFD46 -#define MS_SECTOR_CNT_H 0xFD47 -#define MS_DBUS_H 0xFD48 - -#define SD_CFG1 0xFDA0 -#define SD_CLK_DIVIDE_0 0x00 -#define SD_CLK_DIVIDE_256 0xC0 -#define SD_CLK_DIVIDE_128 0x80 -#define SD_BUS_WIDTH_1BIT 0x00 -#define SD_BUS_WIDTH_4BIT 0x01 -#define SD_BUS_WIDTH_8BIT 0x02 -#define SD_ASYNC_FIFO_NOT_RST 0x10 -#define SD_20_MODE 0x00 -#define SD_DDR_MODE 0x04 -#define SD_30_MODE 0x08 -#define SD_CLK_DIVIDE_MASK 0xC0 -#define SD_CFG2 0xFDA1 -#define SD_CALCULATE_CRC7 0x00 -#define SD_NO_CALCULATE_CRC7 0x80 -#define SD_CHECK_CRC16 0x00 -#define SD_NO_CHECK_CRC16 0x40 -#define SD_NO_CHECK_WAIT_CRC_TO 0x20 -#define SD_WAIT_BUSY_END 0x08 -#define SD_NO_WAIT_BUSY_END 0x00 -#define SD_CHECK_CRC7 0x00 -#define SD_NO_CHECK_CRC7 0x04 -#define SD_RSP_LEN_0 0x00 -#define SD_RSP_LEN_6 0x01 -#define SD_RSP_LEN_17 0x02 -#define SD_RSP_TYPE_R0 0x04 -#define SD_RSP_TYPE_R1 0x01 -#define SD_RSP_TYPE_R1b 0x09 -#define SD_RSP_TYPE_R2 0x02 -#define SD_RSP_TYPE_R3 0x05 -#define SD_RSP_TYPE_R4 0x05 -#define SD_RSP_TYPE_R5 0x01 -#define SD_RSP_TYPE_R6 0x01 -#define SD_RSP_TYPE_R7 0x01 -#define SD_CFG3 0xFDA2 -#define SD_RSP_80CLK_TIMEOUT_EN 0x01 - -#define SD_STAT1 0xFDA3 -#define SD_CRC7_ERR 0x80 -#define SD_CRC16_ERR 0x40 -#define SD_CRC_WRITE_ERR 0x20 -#define SD_CRC_WRITE_ERR_MASK 0x1C -#define GET_CRC_TIME_OUT 0x02 -#define SD_TUNING_COMPARE_ERR 0x01 -#define SD_STAT2 0xFDA4 -#define SD_RSP_80CLK_TIMEOUT 0x01 - -#define SD_BUS_STAT 0xFDA5 -#define SD_CLK_TOGGLE_EN 0x80 -#define SD_CLK_FORCE_STOP 0x40 -#define SD_DAT3_STATUS 0x10 -#define SD_DAT2_STATUS 0x08 -#define SD_DAT1_STATUS 0x04 -#define SD_DAT0_STATUS 0x02 -#define SD_CMD_STATUS 0x01 -#define SD_PAD_CTL 0xFDA6 -#define SD_IO_USING_1V8 0x80 -#define SD_IO_USING_3V3 0x7F -#define TYPE_A_DRIVING 0x00 -#define TYPE_B_DRIVING 0x01 -#define TYPE_C_DRIVING 0x02 -#define TYPE_D_DRIVING 0x03 -#define SD_SAMPLE_POINT_CTL 0xFDA7 -#define DDR_FIX_RX_DAT 0x00 -#define DDR_VAR_RX_DAT 0x80 -#define DDR_FIX_RX_DAT_EDGE 0x00 -#define DDR_FIX_RX_DAT_14_DELAY 0x40 -#define DDR_FIX_RX_CMD 0x00 -#define DDR_VAR_RX_CMD 0x20 -#define DDR_FIX_RX_CMD_POS_EDGE 0x00 -#define DDR_FIX_RX_CMD_14_DELAY 0x10 -#define SD20_RX_POS_EDGE 0x00 -#define SD20_RX_14_DELAY 0x08 -#define SD20_RX_SEL_MASK 0x08 -#define SD_PUSH_POINT_CTL 0xFDA8 -#define DDR_FIX_TX_CMD_DAT 0x00 -#define DDR_VAR_TX_CMD_DAT 0x80 -#define DDR_FIX_TX_DAT_14_TSU 0x00 -#define DDR_FIX_TX_DAT_12_TSU 0x40 -#define DDR_FIX_TX_CMD_NEG_EDGE 0x00 -#define DDR_FIX_TX_CMD_14_AHEAD 0x20 -#define SD20_TX_NEG_EDGE 0x00 -#define SD20_TX_14_AHEAD 0x10 -#define SD20_TX_SEL_MASK 0x10 -#define DDR_VAR_SDCLK_POL_SWAP 0x01 -#define SD_CMD0 0xFDA9 -#define SD_CMD_START 0x40 -#define SD_CMD1 0xFDAA -#define SD_CMD2 0xFDAB -#define SD_CMD3 0xFDAC -#define SD_CMD4 0xFDAD -#define SD_CMD5 0xFDAE -#define SD_BYTE_CNT_L 0xFDAF -#define SD_BYTE_CNT_H 0xFDB0 -#define SD_BLOCK_CNT_L 0xFDB1 -#define SD_BLOCK_CNT_H 0xFDB2 -#define SD_TRANSFER 0xFDB3 -#define SD_TRANSFER_START 0x80 -#define SD_TRANSFER_END 0x40 -#define SD_STAT_IDLE 0x20 -#define SD_TRANSFER_ERR 0x10 -#define SD_TM_NORMAL_WRITE 0x00 -#define SD_TM_AUTO_WRITE_3 0x01 -#define SD_TM_AUTO_WRITE_4 0x02 -#define SD_TM_AUTO_READ_3 0x05 -#define SD_TM_AUTO_READ_4 0x06 -#define SD_TM_CMD_RSP 0x08 -#define SD_TM_AUTO_WRITE_1 0x09 -#define SD_TM_AUTO_WRITE_2 0x0A -#define SD_TM_NORMAL_READ 0x0C -#define SD_TM_AUTO_READ_1 0x0D -#define SD_TM_AUTO_READ_2 0x0E -#define SD_TM_AUTO_TUNING 0x0F -#define SD_CMD_STATE 0xFDB5 -#define SD_CMD_IDLE 0x80 - -#define SD_DATA_STATE 0xFDB6 -#define SD_DATA_IDLE 0x80 - -#define SRCTL 0xFC13 - -#define DCM_DRP_CTL 0xFC23 -#define DCM_RESET 0x08 -#define DCM_LOCKED 0x04 -#define DCM_208M 0x00 -#define DCM_TX 0x01 -#define DCM_RX 0x02 -#define DCM_DRP_TRIG 0xFC24 -#define DRP_START 0x80 -#define DRP_DONE 0x40 -#define DCM_DRP_CFG 0xFC25 -#define DRP_WRITE 0x80 -#define DRP_READ 0x00 -#define DCM_WRITE_ADDRESS_50 0x50 -#define DCM_WRITE_ADDRESS_51 0x51 -#define DCM_READ_ADDRESS_00 0x00 -#define DCM_READ_ADDRESS_51 0x51 -#define DCM_DRP_WR_DATA_L 0xFC26 -#define DCM_DRP_WR_DATA_H 0xFC27 -#define DCM_DRP_RD_DATA_L 0xFC28 -#define DCM_DRP_RD_DATA_H 0xFC29 -#define SD_VPCLK0_CTL 0xFC2A -#define SD_VPCLK1_CTL 0xFC2B -#define PHASE_SELECT_MASK 0x1F -#define SD_DCMPS0_CTL 0xFC2C -#define SD_DCMPS1_CTL 0xFC2D -#define SD_VPTX_CTL SD_VPCLK0_CTL -#define SD_VPRX_CTL SD_VPCLK1_CTL -#define PHASE_CHANGE 0x80 -#define PHASE_NOT_RESET 0x40 -#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL -#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL -#define DCMPS_CHANGE 0x80 -#define DCMPS_CHANGE_DONE 0x40 -#define DCMPS_ERROR 0x20 -#define DCMPS_CURRENT_PHASE 0x1F -#define CARD_CLK_SOURCE 0xFC2E -#define CRC_FIX_CLK (0x00 << 0) -#define CRC_VAR_CLK0 (0x01 << 0) -#define CRC_VAR_CLK1 (0x02 << 0) -#define SD30_FIX_CLK (0x00 << 2) -#define SD30_VAR_CLK0 (0x01 << 2) -#define SD30_VAR_CLK1 (0x02 << 2) -#define SAMPLE_FIX_CLK (0x00 << 4) -#define SAMPLE_VAR_CLK0 (0x01 << 4) -#define SAMPLE_VAR_CLK1 (0x02 << 4) -#define CARD_PWR_CTL 0xFD50 -#define PMOS_STRG_MASK 0x10 -#define PMOS_STRG_800mA 0x10 -#define PMOS_STRG_400mA 0x00 -#define SD_POWER_OFF 0x03 -#define SD_PARTIAL_POWER_ON 0x01 -#define SD_POWER_ON 0x00 -#define SD_POWER_MASK 0x03 -#define MS_POWER_OFF 0x0C -#define MS_PARTIAL_POWER_ON 0x04 -#define MS_POWER_ON 0x00 -#define MS_POWER_MASK 0x0C -#define BPP_POWER_OFF 0x0F -#define BPP_POWER_5_PERCENT_ON 0x0E -#define BPP_POWER_10_PERCENT_ON 0x0C -#define BPP_POWER_15_PERCENT_ON 0x08 -#define BPP_POWER_ON 0x00 -#define BPP_POWER_MASK 0x0F -#define SD_VCC_PARTIAL_POWER_ON 0x02 -#define SD_VCC_POWER_ON 0x00 -#define CARD_CLK_SWITCH 0xFD51 -#define RTL8411B_PACKAGE_MODE 0xFD51 -#define CARD_SHARE_MODE 0xFD52 -#define CARD_SHARE_MASK 0x0F -#define CARD_SHARE_MULTI_LUN 0x00 -#define CARD_SHARE_NORMAL 0x00 -#define CARD_SHARE_48_SD 0x04 -#define CARD_SHARE_48_MS 0x08 -#define CARD_SHARE_BAROSSA_SD 0x01 -#define CARD_SHARE_BAROSSA_MS 0x02 -#define CARD_DRIVE_SEL 0xFD53 -#define MS_DRIVE_8mA (0x01 << 6) -#define MMC_DRIVE_8mA (0x01 << 4) -#define XD_DRIVE_8mA (0x01 << 2) -#define GPIO_DRIVE_8mA 0x01 -#define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\ - XD_DRIVE_8mA | GPIO_DRIVE_8mA) -#define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\ - XD_DRIVE_8mA) -#define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA) - -#define CARD_STOP 0xFD54 -#define SPI_STOP 0x01 -#define XD_STOP 0x02 -#define SD_STOP 0x04 -#define MS_STOP 0x08 -#define SPI_CLR_ERR 0x10 -#define XD_CLR_ERR 0x20 -#define SD_CLR_ERR 0x40 -#define MS_CLR_ERR 0x80 -#define CARD_OE 0xFD55 -#define SD_OUTPUT_EN 0x04 -#define MS_OUTPUT_EN 0x08 -#define CARD_AUTO_BLINK 0xFD56 -#define CARD_GPIO_DIR 0xFD57 -#define CARD_GPIO 0xFD58 -#define CARD_DATA_SOURCE 0xFD5B -#define PINGPONG_BUFFER 0x01 -#define RING_BUFFER 0x00 -#define SD30_CLK_DRIVE_SEL 0xFD5A -#define DRIVER_TYPE_A 0x05 -#define DRIVER_TYPE_B 0x03 -#define DRIVER_TYPE_C 0x02 -#define DRIVER_TYPE_D 0x01 -#define CARD_SELECT 0xFD5C -#define SD_MOD_SEL 2 -#define MS_MOD_SEL 3 -#define SD30_DRIVE_SEL 0xFD5E -#define CFG_DRIVER_TYPE_A 0x02 -#define CFG_DRIVER_TYPE_B 0x03 -#define CFG_DRIVER_TYPE_C 0x01 -#define CFG_DRIVER_TYPE_D 0x00 -#define SD30_CMD_DRIVE_SEL 0xFD5E -#define SD30_DAT_DRIVE_SEL 0xFD5F -#define CARD_CLK_EN 0xFD69 -#define SD_CLK_EN 0x04 -#define MS_CLK_EN 0x08 -#define SDIO_CTRL 0xFD6B -#define CD_PAD_CTL 0xFD73 -#define CD_DISABLE_MASK 0x07 -#define MS_CD_DISABLE 0x04 -#define SD_CD_DISABLE 0x02 -#define XD_CD_DISABLE 0x01 -#define CD_DISABLE 0x07 -#define CD_ENABLE 0x00 -#define MS_CD_EN_ONLY 0x03 -#define SD_CD_EN_ONLY 0x05 -#define XD_CD_EN_ONLY 0x06 -#define FORCE_CD_LOW_MASK 0x38 -#define FORCE_CD_XD_LOW 0x08 -#define FORCE_CD_SD_LOW 0x10 -#define FORCE_CD_MS_LOW 0x20 -#define CD_AUTO_DISABLE 0x40 -#define FPDCTL 0xFC00 -#define SSC_POWER_DOWN 0x01 -#define SD_OC_POWER_DOWN 0x02 -#define ALL_POWER_DOWN 0x07 -#define OC_POWER_DOWN 0x06 -#define PDINFO 0xFC01 - -#define CLK_CTL 0xFC02 -#define CHANGE_CLK 0x01 -#define CLK_LOW_FREQ 0x01 - -#define CLK_DIV 0xFC03 -#define CLK_DIV_1 0x01 -#define CLK_DIV_2 0x02 -#define CLK_DIV_4 0x03 -#define CLK_DIV_8 0x04 -#define CLK_SEL 0xFC04 - -#define SSC_DIV_N_0 0xFC0F -#define SSC_DIV_N_1 0xFC10 -#define SSC_CTL1 0xFC11 -#define SSC_RSTB 0x80 -#define SSC_8X_EN 0x40 -#define SSC_FIX_FRAC 0x20 -#define SSC_SEL_1M 0x00 -#define SSC_SEL_2M 0x08 -#define SSC_SEL_4M 0x10 -#define SSC_SEL_8M 0x18 -#define SSC_CTL2 0xFC12 -#define SSC_DEPTH_MASK 0x07 -#define SSC_DEPTH_DISALBE 0x00 -#define SSC_DEPTH_4M 0x01 -#define SSC_DEPTH_2M 0x02 -#define SSC_DEPTH_1M 0x03 -#define SSC_DEPTH_500K 0x04 -#define SSC_DEPTH_250K 0x05 -#define RCCTL 0xFC14 - -#define FPGA_PULL_CTL 0xFC1D -#define OLT_LED_CTL 0xFC1E -#define GPIO_CTL 0xFC1F - -#define LDO_CTL 0xFC1E -#define BPP_ASIC_1V7 0x00 -#define BPP_ASIC_1V8 0x01 -#define BPP_ASIC_1V9 0x02 -#define BPP_ASIC_2V0 0x03 -#define BPP_ASIC_2V7 0x04 -#define BPP_ASIC_2V8 0x05 -#define BPP_ASIC_3V2 0x06 -#define BPP_ASIC_3V3 0x07 -#define BPP_REG_TUNED18 0x07 -#define BPP_TUNED18_SHIFT_8402 5 -#define BPP_TUNED18_SHIFT_8411 4 -#define BPP_PAD_MASK 0x04 -#define BPP_PAD_3V3 0x04 -#define BPP_PAD_1V8 0x00 -#define BPP_LDO_POWB 0x03 -#define BPP_LDO_ON 0x00 -#define BPP_LDO_SUSPEND 0x02 -#define BPP_LDO_OFF 0x03 -#define SYS_VER 0xFC32 - -#define CARD_PULL_CTL1 0xFD60 -#define CARD_PULL_CTL2 0xFD61 -#define CARD_PULL_CTL3 0xFD62 -#define CARD_PULL_CTL4 0xFD63 -#define CARD_PULL_CTL5 0xFD64 -#define CARD_PULL_CTL6 0xFD65 - -/* PCI Express Related Registers */ -#define IRQEN0 0xFE20 -#define IRQSTAT0 0xFE21 -#define DMA_DONE_INT 0x80 -#define SUSPEND_INT 0x40 -#define LINK_RDY_INT 0x20 -#define LINK_DOWN_INT 0x10 -#define IRQEN1 0xFE22 -#define IRQSTAT1 0xFE23 -#define TLPRIEN 0xFE24 -#define TLPRISTAT 0xFE25 -#define TLPTIEN 0xFE26 -#define TLPTISTAT 0xFE27 -#define DMATC0 0xFE28 -#define DMATC1 0xFE29 -#define DMATC2 0xFE2A -#define DMATC3 0xFE2B -#define DMACTL 0xFE2C -#define DMA_RST 0x80 -#define DMA_BUSY 0x04 -#define DMA_DIR_TO_CARD 0x00 -#define DMA_DIR_FROM_CARD 0x02 -#define DMA_EN 0x01 -#define DMA_128 (0 << 4) -#define DMA_256 (1 << 4) -#define DMA_512 (2 << 4) -#define DMA_1024 (3 << 4) -#define DMA_PACK_SIZE_MASK 0x30 -#define BCTL 0xFE2D -#define RBBC0 0xFE2E -#define RBBC1 0xFE2F -#define RBDAT 0xFE30 -#define RBCTL 0xFE34 -#define CFGADDR0 0xFE35 -#define CFGADDR1 0xFE36 -#define CFGDATA0 0xFE37 -#define CFGDATA1 0xFE38 -#define CFGDATA2 0xFE39 -#define CFGDATA3 0xFE3A -#define CFGRWCTL 0xFE3B -#define PHYRWCTL 0xFE3C -#define PHYDATA0 0xFE3D -#define PHYDATA1 0xFE3E -#define PHYADDR 0xFE3F -#define MSGRXDATA0 0xFE40 -#define MSGRXDATA1 0xFE41 -#define MSGRXDATA2 0xFE42 -#define MSGRXDATA3 0xFE43 -#define MSGTXDATA0 0xFE44 -#define MSGTXDATA1 0xFE45 -#define MSGTXDATA2 0xFE46 -#define MSGTXDATA3 0xFE47 -#define MSGTXCTL 0xFE48 -#define LTR_CTL 0xFE4A -#define LTR_TX_EN_MASK BIT(7) -#define LTR_TX_EN_1 BIT(7) -#define LTR_TX_EN_0 0 -#define LTR_LATENCY_MODE_MASK BIT(6) -#define LTR_LATENCY_MODE_HW 0 -#define LTR_LATENCY_MODE_SW BIT(6) -#define OBFF_CFG 0xFE4C - -#define CDRESUMECTL 0xFE52 -#define WAKE_SEL_CTL 0xFE54 -#define PCLK_CTL 0xFE55 -#define PCLK_MODE_SEL 0x20 -#define PME_FORCE_CTL 0xFE56 - -#define ASPM_FORCE_CTL 0xFE57 -#define FORCE_ASPM_CTL0 0x10 -#define FORCE_ASPM_VAL_MASK 0x03 -#define FORCE_ASPM_L1_EN 0x02 -#define FORCE_ASPM_L0_EN 0x01 -#define FORCE_ASPM_NO_ASPM 0x00 -#define PM_CLK_FORCE_CTL 0xFE58 -#define FUNC_FORCE_CTL 0xFE59 -#define FUNC_FORCE_UPME_XMT_DBG 0x02 -#define PERST_GLITCH_WIDTH 0xFE5C -#define CHANGE_LINK_STATE 0xFE5B -#define RESET_LOAD_REG 0xFE5E -#define EFUSE_CONTENT 0xFE5F -#define HOST_SLEEP_STATE 0xFE60 -#define HOST_ENTER_S1 1 -#define HOST_ENTER_S3 2 - -#define SDIO_CFG 0xFE70 -#define PM_EVENT_DEBUG 0xFE71 -#define PME_DEBUG_0 0x08 -#define NFTS_TX_CTRL 0xFE72 - -#define PWR_GATE_CTRL 0xFE75 -#define PWR_GATE_EN 0x01 -#define LDO3318_PWR_MASK 0x06 -#define LDO_ON 0x00 -#define LDO_SUSPEND 0x04 -#define LDO_OFF 0x06 -#define PWD_SUSPEND_EN 0xFE76 -#define LDO_PWR_SEL 0xFE78 - -#define L1SUB_CONFIG1 0xFE8D -#define L1SUB_CONFIG2 0xFE8E -#define L1SUB_AUTO_CFG 0x02 -#define L1SUB_CONFIG3 0xFE8F -#define L1OFF_MBIAS2_EN_5250 BIT(7) - -#define DUMMY_REG_RESET_0 0xFE90 - -#define AUTOLOAD_CFG_BASE 0xFF00 -#define PETXCFG 0xFF03 -#define FORCE_CLKREQ_DELINK_MASK BIT(7) -#define FORCE_CLKREQ_LOW 0x80 -#define FORCE_CLKREQ_HIGH 0x00 - -#define PM_CTRL1 0xFF44 -#define CD_RESUME_EN_MASK 0xF0 - -#define PM_CTRL2 0xFF45 -#define PM_CTRL3 0xFF46 -#define SDIO_SEND_PME_EN 0x80 -#define FORCE_RC_MODE_ON 0x40 -#define FORCE_RX50_LINK_ON 0x20 -#define D3_DELINK_MODE_EN 0x10 -#define USE_PESRTB_CTL_DELINK 0x08 -#define DELAY_PIN_WAKE 0x04 -#define RESET_PIN_WAKE 0x02 -#define PM_WAKE_EN 0x01 -#define PM_CTRL4 0xFF47 - -/* Memory mapping */ -#define SRAM_BASE 0xE600 -#define RBUF_BASE 0xF400 -#define PPBUF_BASE1 0xF800 -#define PPBUF_BASE2 0xFA00 -#define IMAGE_FLAG_ADDR0 0xCE80 -#define IMAGE_FLAG_ADDR1 0xCE81 - -#define RREF_CFG 0xFF6C -#define RREF_VBGSEL_MASK 0x38 -#define RREF_VBGSEL_1V25 0x28 - -#define OOBS_CONFIG 0xFF6E -#define OOBS_AUTOK_DIS 0x80 -#define OOBS_VAL_MASK 0x1F - -#define LDO_DV18_CFG 0xFF70 -#define LDO_DV18_SR_MASK 0xC0 -#define LDO_DV18_SR_DF 0x40 - -#define LDO_CONFIG2 0xFF71 -#define LDO_D3318_MASK 0x07 -#define LDO_D3318_33V 0x07 -#define LDO_D3318_18V 0x02 - -#define LDO_VCC_CFG0 0xFF72 -#define LDO_VCC_LMTVTH_MASK 0x30 -#define LDO_VCC_LMTVTH_2A 0x10 - -#define LDO_VCC_CFG1 0xFF73 -#define LDO_VCC_REF_TUNE_MASK 0x30 -#define LDO_VCC_REF_1V2 0x20 -#define LDO_VCC_TUNE_MASK 0x07 -#define LDO_VCC_1V8 0x04 -#define LDO_VCC_3V3 0x07 -#define LDO_VCC_LMT_EN 0x08 - -#define LDO_VIO_CFG 0xFF75 -#define LDO_VIO_SR_MASK 0xC0 -#define LDO_VIO_SR_DF 0x40 -#define LDO_VIO_REF_TUNE_MASK 0x30 -#define LDO_VIO_REF_1V2 0x20 -#define LDO_VIO_TUNE_MASK 0x07 -#define LDO_VIO_1V7 0x03 -#define LDO_VIO_1V8 0x04 -#define LDO_VIO_3V3 0x07 - -#define LDO_DV12S_CFG 0xFF76 -#define LDO_REF12_TUNE_MASK 0x18 -#define LDO_REF12_TUNE_DF 0x10 -#define LDO_D12_TUNE_MASK 0x07 -#define LDO_D12_TUNE_DF 0x04 - -#define LDO_AV12S_CFG 0xFF77 -#define LDO_AV12S_TUNE_MASK 0x07 -#define LDO_AV12S_TUNE_DF 0x04 - -#define SD40_LDO_CTL1 0xFE7D -#define SD40_VIO_TUNE_MASK 0x70 -#define SD40_VIO_TUNE_1V7 0x30 -#define SD_VIO_LDO_1V8 0x40 -#define SD_VIO_LDO_3V3 0x70 - -/* Phy register */ -#define PHY_PCR 0x00 -#define PHY_PCR_FORCE_CODE 0xB000 -#define PHY_PCR_OOBS_CALI_50 0x0800 -#define PHY_PCR_OOBS_VCM_08 0x0200 -#define PHY_PCR_OOBS_SEN_90 0x0040 -#define PHY_PCR_RSSI_EN 0x0002 -#define PHY_PCR_RX10K 0x0001 - -#define PHY_RCR0 0x01 -#define PHY_RCR1 0x02 -#define PHY_RCR1_ADP_TIME_4 0x0400 -#define PHY_RCR1_VCO_COARSE 0x001F -#define PHY_RCR1_INIT_27S 0x0A1F -#define PHY_SSCCR2 0x02 -#define PHY_SSCCR2_PLL_NCODE 0x0A00 -#define PHY_SSCCR2_TIME0 0x001C -#define PHY_SSCCR2_TIME2_WIDTH 0x0003 - -#define PHY_RCR2 0x03 -#define PHY_RCR2_EMPHASE_EN 0x8000 -#define PHY_RCR2_NADJR 0x4000 -#define PHY_RCR2_CDR_SR_2 0x0100 -#define PHY_RCR2_FREQSEL_12 0x0040 -#define PHY_RCR2_CDR_SC_12P 0x0010 -#define PHY_RCR2_CALIB_LATE 0x0002 -#define PHY_RCR2_INIT_27S 0xC152 -#define PHY_SSCCR3 0x03 -#define PHY_SSCCR3_STEP_IN 0x2740 -#define PHY_SSCCR3_CHECK_DELAY 0x0008 -#define _PHY_ANA03 0x03 -#define _PHY_ANA03_TIMER_MAX 0x2700 -#define _PHY_ANA03_OOBS_DEB_EN 0x0040 -#define _PHY_CMU_DEBUG_EN 0x0008 - -#define PHY_RTCR 0x04 -#define PHY_RDR 0x05 -#define PHY_RDR_RXDSEL_1_9 0x4000 -#define PHY_SSC_AUTO_PWD 0x0600 -#define PHY_TCR0 0x06 -#define PHY_TCR1 0x07 -#define PHY_TUNE 0x08 -#define PHY_TUNE_TUNEREF_1_0 0x4000 -#define PHY_TUNE_VBGSEL_1252 0x0C00 -#define PHY_TUNE_SDBUS_33 0x0200 -#define PHY_TUNE_TUNED18 0x01C0 -#define PHY_TUNE_TUNED12 0X0020 -#define PHY_TUNE_TUNEA12 0x0004 -#define PHY_TUNE_VOLTAGE_MASK 0xFC3F -#define PHY_TUNE_VOLTAGE_3V3 0x03C0 -#define PHY_TUNE_D18_1V8 0x0100 -#define PHY_TUNE_D18_1V7 0x0080 -#define PHY_ANA08 0x08 -#define PHY_ANA08_RX_EQ_DCGAIN 0x5000 -#define PHY_ANA08_SEL_RX_EN 0x0400 -#define PHY_ANA08_RX_EQ_VAL 0x03C0 -#define PHY_ANA08_SCP 0x0020 -#define PHY_ANA08_SEL_IPI 0x0004 - -#define PHY_IMR 0x09 -#define PHY_BPCR 0x0A -#define PHY_BPCR_IBRXSEL 0x0400 -#define PHY_BPCR_IBTXSEL 0x0100 -#define PHY_BPCR_IB_FILTER 0x0080 -#define PHY_BPCR_CMIRROR_EN 0x0040 - -#define PHY_BIST 0x0B -#define PHY_RAW_L 0x0C -#define PHY_RAW_H 0x0D -#define PHY_RAW_DATA 0x0E -#define PHY_HOST_CLK_CTRL 0x0F -#define PHY_DMR 0x10 -#define PHY_BACR 0x11 -#define PHY_BACR_BASIC_MASK 0xFFF3 -#define PHY_IER 0x12 -#define PHY_BCSR 0x13 -#define PHY_BPR 0x14 -#define PHY_BPNR2 0x15 -#define PHY_BPNR 0x16 -#define PHY_BRNR2 0x17 -#define PHY_BENR 0x18 -#define PHY_REV 0x19 -#define PHY_REV_RESV 0xE000 -#define PHY_REV_RXIDLE_LATCHED 0x1000 -#define PHY_REV_P1_EN 0x0800 -#define PHY_REV_RXIDLE_EN 0x0400 -#define PHY_REV_CLKREQ_TX_EN 0x0200 -#define PHY_REV_CLKREQ_RX_EN 0x0100 -#define PHY_REV_CLKREQ_DT_1_0 0x0040 -#define PHY_REV_STOP_CLKRD 0x0020 -#define PHY_REV_RX_PWST 0x0008 -#define PHY_REV_STOP_CLKWR 0x0004 -#define _PHY_REV0 0x19 -#define _PHY_REV0_FILTER_OUT 0x3800 -#define _PHY_REV0_CDR_BYPASS_PFD 0x0100 -#define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002 - -#define PHY_FLD0 0x1A -#define PHY_ANA1A 0x1A -#define PHY_ANA1A_TXR_LOOPBACK 0x2000 -#define PHY_ANA1A_RXT_BIST 0x0500 -#define PHY_ANA1A_TXR_BIST 0x0040 -#define PHY_ANA1A_REV 0x0006 -#define PHY_FLD0_INIT_27S 0x2546 -#define PHY_FLD1 0x1B -#define PHY_FLD2 0x1C -#define PHY_FLD3 0x1D -#define PHY_FLD3_TIMER_4 0x0800 -#define PHY_FLD3_TIMER_6 0x0020 -#define PHY_FLD3_RXDELINK 0x0004 -#define PHY_FLD3_INIT_27S 0x0004 -#define PHY_ANA1D 0x1D -#define PHY_ANA1D_DEBUG_ADDR 0x0004 -#define _PHY_FLD0 0x1D -#define _PHY_FLD0_CLK_REQ_20C 0x8000 -#define _PHY_FLD0_RX_IDLE_EN 0x1000 -#define _PHY_FLD0_BIT_ERR_RSTN 0x0800 -#define _PHY_FLD0_BER_COUNT 0x01E0 -#define _PHY_FLD0_BER_TIMER 0x001E -#define _PHY_FLD0_CHECK_EN 0x0001 - -#define PHY_FLD4 0x1E -#define PHY_FLD4_FLDEN_SEL 0x4000 -#define PHY_FLD4_REQ_REF 0x2000 -#define PHY_FLD4_RXAMP_OFF 0x1000 -#define PHY_FLD4_REQ_ADDA 0x0800 -#define PHY_FLD4_BER_COUNT 0x00E0 -#define PHY_FLD4_BER_TIMER 0x000A -#define PHY_FLD4_BER_CHK_EN 0x0001 -#define PHY_FLD4_INIT_27S 0x5C7F -#define PHY_DIG1E 0x1E -#define PHY_DIG1E_REV 0x4000 -#define PHY_DIG1E_D0_X_D1 0x1000 -#define PHY_DIG1E_RX_ON_HOST 0x0800 -#define PHY_DIG1E_RCLK_REF_HOST 0x0400 -#define PHY_DIG1E_RCLK_TX_EN_KEEP 0x0040 -#define PHY_DIG1E_RCLK_TX_TERM_KEEP 0x0020 |