diff options
Diffstat (limited to 'include')
21 files changed, 2558 insertions, 2 deletions
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h index 8279f427c60f..0ae6f5a75d2a 100644 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ b/include/dt-bindings/clk/exynos-audss-clk.h @@ -19,7 +19,8 @@ #define EXYNOS_SCLK_I2S 7 #define EXYNOS_PCM_BUS 8 #define EXYNOS_SCLK_PCM 9 +#define EXYNOS_ADMA 10 -#define EXYNOS_AUDSS_MAX_CLKS 10 +#define EXYNOS_AUDSS_MAX_CLKS 11 #endif diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h new file mode 100644 index 000000000000..75aff336dfb0 --- /dev/null +++ b/include/dt-bindings/clock/exynos4.h @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * Author: Andrzej Haja <a.hajda@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Exynos4 clock controller. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H +#define _DT_BINDINGS_CLOCK_EXYNOS_4_H + +/* core clocks */ +#define CLK_XXTI 1 +#define CLK_XUSBXTI 2 +#define CLK_FIN_PLL 3 +#define CLK_FOUT_APLL 4 +#define CLK_FOUT_MPLL 5 +#define CLK_FOUT_EPLL 6 +#define CLK_FOUT_VPLL 7 +#define CLK_SCLK_APLL 8 +#define CLK_SCLK_MPLL 9 +#define CLK_SCLK_EPLL 10 +#define CLK_SCLK_VPLL 11 +#define CLK_ARM_CLK 12 +#define CLK_ACLK200 13 +#define CLK_ACLK100 14 +#define CLK_ACLK160 15 +#define CLK_ACLK133 16 +#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ +#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ +#define CLK_MOUT_CORE 19 +#define CLK_MOUT_APLL 20 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_FIMC0 128 +#define CLK_SCLK_FIMC1 129 +#define CLK_SCLK_FIMC2 130 +#define CLK_SCLK_FIMC3 131 +#define CLK_SCLK_CAM0 132 +#define CLK_SCLK_CAM1 133 +#define CLK_SCLK_CSIS0 134 +#define CLK_SCLK_CSIS1 135 +#define CLK_SCLK_HDMI 136 +#define CLK_SCLK_MIXER 137 +#define CLK_SCLK_DAC 138 +#define CLK_SCLK_PIXEL 139 +#define CLK_SCLK_FIMD0 140 +#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ +#define CLK_SCLK_MDNIE_PWM0 142 +#define CLK_SCLK_MIPI0 143 +#define CLK_SCLK_AUDIO0 144 +#define CLK_SCLK_MMC0 145 +#define CLK_SCLK_MMC1 146 +#define CLK_SCLK_MMC2 147 +#define CLK_SCLK_MMC3 148 +#define CLK_SCLK_MMC4 149 +#define CLK_SCLK_SATA 150 /* Exynos4210 only */ +#define CLK_SCLK_UART0 151 +#define CLK_SCLK_UART1 152 +#define CLK_SCLK_UART2 153 +#define CLK_SCLK_UART3 154 +#define CLK_SCLK_UART4 155 +#define CLK_SCLK_AUDIO1 156 +#define CLK_SCLK_AUDIO2 157 +#define CLK_SCLK_SPDIF 158 +#define CLK_SCLK_SPI0 159 +#define CLK_SCLK_SPI1 160 +#define CLK_SCLK_SPI2 161 +#define CLK_SCLK_SLIMBUS 162 +#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ +#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ +#define CLK_SCLK_PCM1 165 +#define CLK_SCLK_PCM2 166 +#define CLK_SCLK_I2S1 167 +#define CLK_SCLK_I2S2 168 +#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ +#define CLK_SCLK_MFC 170 +#define CLK_SCLK_PCM0 171 +#define CLK_SCLK_G3D 172 +#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ +#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ +#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ +#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ +#define CLK_SCLK_FIMG2D 177 + +/* gate clocks */ +#define CLK_FIMC0 256 +#define CLK_FIMC1 257 +#define CLK_FIMC2 258 +#define CLK_FIMC3 259 +#define CLK_CSIS0 260 +#define CLK_CSIS1 261 +#define CLK_JPEG 262 +#define CLK_SMMU_FIMC0 263 +#define CLK_SMMU_FIMC1 264 +#define CLK_SMMU_FIMC2 265 +#define CLK_SMMU_FIMC3 266 +#define CLK_SMMU_JPEG 267 +#define CLK_VP 268 +#define CLK_MIXER 269 +#define CLK_TVENC 270 /* Exynos4210 only */ +#define CLK_HDMI 271 +#define CLK_SMMU_TV 272 +#define CLK_MFC 273 +#define CLK_SMMU_MFCL 274 +#define CLK_SMMU_MFCR 275 +#define CLK_G3D 276 +#define CLK_G2D 277 +#define CLK_ROTATOR 278 /* Exynos4210 only */ +#define CLK_MDMA 279 /* Exynos4210 only */ +#define CLK_SMMU_G2D 280 /* Exynos4210 only */ +#define CLK_SMMU_ROTATOR 281 /* Exynos4210 only */ +#define CLK_SMMU_MDMA 282 /* Exynos4210 only */ +#define CLK_FIMD0 283 +#define CLK_MIE0 284 +#define CLK_MDNIE0 285 /* Exynos4412 only */ +#define CLK_DSIM0 286 +#define CLK_SMMU_FIMD0 287 +#define CLK_FIMD1 288 /* Exynos4210 only */ +#define CLK_MIE1 289 /* Exynos4210 only */ +#define CLK_DSIM1 290 /* Exynos4210 only */ +#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ +#define CLK_PDMA0 292 +#define CLK_PDMA1 293 +#define CLK_PCIE_PHY 294 +#define CLK_SATA_PHY 295 /* Exynos4210 only */ +#define CLK_TSI 296 +#define CLK_SDMMC0 297 +#define CLK_SDMMC1 298 +#define CLK_SDMMC2 299 +#define CLK_SDMMC3 300 +#define CLK_SDMMC4 301 +#define CLK_SATA 302 /* Exynos4210 only */ +#define CLK_SROMC 303 +#define CLK_USB_HOST 304 +#define CLK_USB_DEVICE 305 +#define CLK_PCIE 306 +#define CLK_ONENAND 307 +#define CLK_NFCON 308 +#define CLK_SMMU_PCIE 309 +#define CLK_GPS 310 +#define CLK_SMMU_GPS 311 +#define CLK_UART0 312 +#define CLK_UART1 313 +#define CLK_UART2 314 +#define CLK_UART3 315 +#define CLK_UART4 316 +#define CLK_I2C0 317 +#define CLK_I2C1 318 +#define CLK_I2C2 319 +#define CLK_I2C3 320 +#define CLK_I2C4 321 +#define CLK_I2C5 322 +#define CLK_I2C6 323 +#define CLK_I2C7 324 +#define CLK_I2C_HDMI 325 +#define CLK_TSADC 326 +#define CLK_SPI0 327 +#define CLK_SPI1 328 +#define CLK_SPI2 329 +#define CLK_I2S1 330 +#define CLK_I2S2 331 +#define CLK_PCM0 332 +#define CLK_I2S0 333 +#define CLK_PCM1 334 +#define CLK_PCM2 335 +#define CLK_PWM 336 +#define CLK_SLIMBUS 337 +#define CLK_SPDIF 338 +#define CLK_AC97 339 +#define CLK_MODEMIF 340 +#define CLK_CHIPID 341 +#define CLK_SYSREG 342 +#define CLK_HDMI_CEC 343 +#define CLK_MCT 344 +#define CLK_WDT 345 +#define CLK_RTC 346 +#define CLK_KEYIF 347 +#define CLK_AUDSS 348 +#define CLK_MIPI_HSI 349 /* Exynos4210 only */ +#define CLK_MDMA2 350 /* Exynos4210 only */ +#define CLK_PIXELASYNCM0 351 +#define CLK_PIXELASYNCM1 352 +#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ +#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */ +#define CLK_PPMUISPX 355 /* Exynos4x12 only */ +#define CLK_PPMUISPMX 356 /* Exynos4x12 only */ +#define CLK_FIMC_ISP 357 /* Exynos4x12 only */ +#define CLK_FIMC_DRC 358 /* Exynos4x12 only */ +#define CLK_FIMC_FD 359 /* Exynos4x12 only */ +#define CLK_MCUISP 360 /* Exynos4x12 only */ +#define CLK_GICISP 361 /* Exynos4x12 only */ +#define CLK_SMMU_ISP 362 /* Exynos4x12 only */ +#define CLK_SMMU_DRC 363 /* Exynos4x12 only */ +#define CLK_SMMU_FD 364 /* Exynos4x12 only */ +#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */ +#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */ +#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */ +#define CLK_MPWM_ISP 368 /* Exynos4x12 only */ +#define CLK_I2C0_ISP 369 /* Exynos4x12 only */ +#define CLK_I2C1_ISP 370 /* Exynos4x12 only */ +#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */ +#define CLK_PWM_ISP 372 /* Exynos4x12 only */ +#define CLK_WDT_ISP 373 /* Exynos4x12 only */ +#define CLK_UART_ISP 374 /* Exynos4x12 only */ +#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */ +#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */ +#define CLK_SPI0_ISP 377 /* Exynos4x12 only */ +#define CLK_SPI1_ISP 378 /* Exynos4x12 only */ +#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ +#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ +#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ +#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ +#define CLK_TMU_APBIF 383 + +/* mux clocks */ +#define CLK_MOUT_FIMC0 384 +#define CLK_MOUT_FIMC1 385 +#define CLK_MOUT_FIMC2 386 +#define CLK_MOUT_FIMC3 387 +#define CLK_MOUT_CAM0 388 +#define CLK_MOUT_CAM1 389 +#define CLK_MOUT_CSIS0 390 +#define CLK_MOUT_CSIS1 391 +#define CLK_MOUT_G3D0 392 +#define CLK_MOUT_G3D1 393 +#define CLK_MOUT_G3D 394 +#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ + +/* div clocks */ +#define CLK_DIV_ISP0 450 /* Exynos4x12 only */ +#define CLK_DIV_ISP1 451 /* Exynos4x12 only */ +#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */ +#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ +#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ +#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ + +/* must be greater than maximal clock id */ +#define CLK_NR_CLKS 456 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h new file mode 100644 index 000000000000..922f2dca9bf0 --- /dev/null +++ b/include/dt-bindings/clock/exynos5250.h @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * Author: Andrzej Haja <a.hajda@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Exynos5250 clock controller. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H + +/* core clocks */ +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_MPLL 3 +#define CLK_FOUT_BPLL 4 +#define CLK_FOUT_GPLL 5 +#define CLK_FOUT_CPLL 6 +#define CLK_FOUT_EPLL 7 +#define CLK_FOUT_VPLL 8 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_CAM_BAYER 128 +#define CLK_SCLK_CAM0 129 +#define CLK_SCLK_CAM1 130 +#define CLK_SCLK_GSCL_WA 131 +#define CLK_SCLK_GSCL_WB 132 +#define CLK_SCLK_FIMD1 133 +#define CLK_SCLK_MIPI1 134 +#define CLK_SCLK_DP 135 +#define CLK_SCLK_HDMI 136 +#define CLK_SCLK_PIXEL 137 +#define CLK_SCLK_AUDIO0 138 +#define CLK_SCLK_MMC0 139 +#define CLK_SCLK_MMC1 140 +#define CLK_SCLK_MMC2 141 +#define CLK_SCLK_MMC3 142 +#define CLK_SCLK_SATA 143 +#define CLK_SCLK_USB3 144 +#define CLK_SCLK_JPEG 145 +#define CLK_SCLK_UART0 146 +#define CLK_SCLK_UART1 147 +#define CLK_SCLK_UART2 148 +#define CLK_SCLK_UART3 149 +#define CLK_SCLK_PWM 150 +#define CLK_SCLK_AUDIO1 151 +#define CLK_SCLK_AUDIO2 152 +#define CLK_SCLK_SPDIF 153 +#define CLK_SCLK_SPI0 154 +#define CLK_SCLK_SPI1 155 +#define CLK_SCLK_SPI2 156 +#define CLK_DIV_I2S1 157 +#define CLK_DIV_I2S2 158 +#define CLK_SCLK_HDMIPHY 159 +#define CLK_DIV_PCM0 160 + +/* gate clocks */ +#define CLK_GSCL0 256 +#define CLK_GSCL1 257 +#define CLK_GSCL2 258 +#define CLK_GSCL3 259 +#define CLK_GSCL_WA 260 +#define CLK_GSCL_WB 261 +#define CLK_SMMU_GSCL0 262 +#define CLK_SMMU_GSCL1 263 +#define CLK_SMMU_GSCL2 264 +#define CLK_SMMU_GSCL3 265 +#define CLK_MFC 266 +#define CLK_SMMU_MFCL 267 +#define CLK_SMMU_MFCR 268 +#define CLK_ROTATOR 269 +#define CLK_JPEG 270 +#define CLK_MDMA1 271 +#define CLK_SMMU_ROTATOR 272 +#define CLK_SMMU_JPEG 273 +#define CLK_SMMU_MDMA1 274 +#define CLK_PDMA0 275 +#define CLK_PDMA1 276 +#define CLK_SATA 277 +#define CLK_USBOTG 278 +#define CLK_MIPI_HSI 279 +#define CLK_SDMMC0 280 +#define CLK_SDMMC1 281 +#define CLK_SDMMC2 282 +#define CLK_SDMMC3 283 +#define CLK_SROMC 284 +#define CLK_USB2 285 +#define CLK_USB3 286 +#define CLK_SATA_PHYCTRL 287 +#define CLK_SATA_PHYI2C 288 +#define CLK_UART0 289 +#define CLK_UART1 290 +#define CLK_UART2 291 +#define CLK_UART3 292 +#define CLK_UART4 293 +#define CLK_I2C0 294 +#define CLK_I2C1 295 +#define CLK_I2C2 296 +#define CLK_I2C3 297 +#define CLK_I2C4 298 +#define CLK_I2C5 299 +#define CLK_I2C6 300 +#define CLK_I2C7 301 +#define CLK_I2C_HDMI 302 +#define CLK_ADC 303 +#define CLK_SPI0 304 +#define CLK_SPI1 305 +#define CLK_SPI2 306 +#define CLK_I2S1 307 +#define CLK_I2S2 308 +#define CLK_PCM1 309 +#define CLK_PCM2 310 +#define CLK_PWM 311 +#define CLK_SPDIF 312 +#define CLK_AC97 313 +#define CLK_HSI2C0 314 +#define CLK_HSI2C1 315 +#define CLK_HSI2C2 316 +#define CLK_HSI2C3 317 +#define CLK_CHIPID 318 +#define CLK_SYSREG 319 +#define CLK_PMU 320 +#define CLK_CMU_TOP 321 +#define CLK_CMU_CORE 322 +#define CLK_CMU_MEM 323 +#define CLK_TZPC0 324 +#define CLK_TZPC1 325 +#define CLK_TZPC2 326 +#define CLK_TZPC3 327 +#define CLK_TZPC4 328 +#define CLK_TZPC5 329 +#define CLK_TZPC6 330 +#define CLK_TZPC7 331 +#define CLK_TZPC8 332 +#define CLK_TZPC9 333 +#define CLK_HDMI_CEC 334 +#define CLK_MCT 335 +#define CLK_WDT 336 +#define CLK_RTC 337 +#define CLK_TMU 338 +#define CLK_FIMD1 339 +#define CLK_MIE1 340 +#define CLK_DSIM0 341 +#define CLK_DP 342 +#define CLK_MIXER 343 +#define CLK_HDMI 344 +#define CLK_G2D 345 +#define CLK_MDMA0 346 +#define CLK_SMMU_MDMA0 347 + +/* mux clocks */ +#define CLK_MOUT_HDMI 1024 + +/* must be greater than maximal clock id */ +#define CLK_NR_CLKS 1025 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h new file mode 100644 index 000000000000..5eefd8813f02 --- /dev/null +++ b/include/dt-bindings/clock/exynos5420.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * Author: Andrzej Haja <a.hajda@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Exynos5420 clock controller. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H + +/* core clocks */ +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_CPLL 3 +#define CLK_FOUT_DPLL 4 +#define CLK_FOUT_EPLL 5 +#define CLK_FOUT_RPLL 6 +#define CLK_FOUT_IPLL 7 +#define CLK_FOUT_SPLL 8 +#define CLK_FOUT_VPLL 9 +#define CLK_FOUT_MPLL 10 +#define CLK_FOUT_BPLL 11 +#define CLK_FOUT_KPLL 12 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_UART0 128 +#define CLK_SCLK_UART1 129 +#define CLK_SCLK_UART2 130 +#define CLK_SCLK_UART3 131 +#define CLK_SCLK_MMC0 132 +#define CLK_SCLK_MMC1 133 +#define CLK_SCLK_MMC2 134 +#define CLK_SCLK_SPI0 135 +#define CLK_SCLK_SPI1 136 +#define CLK_SCLK_SPI2 137 +#define CLK_SCLK_I2S1 138 +#define CLK_SCLK_I2S2 139 +#define CLK_SCLK_PCM1 140 +#define CLK_SCLK_PCM2 141 +#define CLK_SCLK_SPDIF 142 +#define CLK_SCLK_HDMI 143 +#define CLK_SCLK_PIXEL 144 +#define CLK_SCLK_DP1 145 +#define CLK_SCLK_MIPI1 146 +#define CLK_SCLK_FIMD1 147 +#define CLK_SCLK_MAUDIO0 148 +#define CLK_SCLK_MAUPCM0 149 +#define CLK_SCLK_USBD300 150 +#define CLK_SCLK_USBD301 151 +#define CLK_SCLK_USBPHY300 152 +#define CLK_SCLK_USBPHY301 153 +#define CLK_SCLK_UNIPRO 154 +#define CLK_SCLK_PWM 155 +#define CLK_SCLK_GSCL_WA 156 +#define CLK_SCLK_GSCL_WB 157 +#define CLK_SCLK_HDMIPHY 158 + +/* gate clocks */ +#define CLK_ACLK66_PERIC 256 +#define CLK_UART0 257 +#define CLK_UART1 258 +#define CLK_UART2 259 +#define CLK_UART3 260 +#define CLK_I2C0 261 +#define CLK_I2C1 262 +#define CLK_I2C2 263 +#define CLK_I2C3 264 +#define CLK_I2C4 265 +#define CLK_I2C5 266 +#define CLK_I2C6 267 +#define CLK_I2C7 268 +#define CLK_I2C_HDMI 269 +#define CLK_TSADC 270 +#define CLK_SPI0 271 +#define CLK_SPI1 272 +#define CLK_SPI2 273 +#define CLK_KEYIF 274 +#define CLK_I2S1 275 +#define CLK_I2S2 276 +#define CLK_PCM1 277 +#define CLK_PCM2 278 +#define CLK_PWM 279 +#define CLK_SPDIF 280 +#define CLK_I2C8 281 +#define CLK_I2C9 282 +#define CLK_I2C10 283 +#define CLK_ACLK66_PSGEN 300 +#define CLK_CHIPID 301 +#define CLK_SYSREG 302 +#define CLK_TZPC0 303 +#define CLK_TZPC1 304 +#define CLK_TZPC2 305 +#define CLK_TZPC3 306 +#define CLK_TZPC4 307 +#define CLK_TZPC5 308 +#define CLK_TZPC6 309 +#define CLK_TZPC7 310 +#define CLK_TZPC8 311 +#define CLK_TZPC9 312 +#define CLK_HDMI_CEC 313 +#define CLK_SECKEY 314 +#define CLK_MCT 315 +#define CLK_WDT 316 +#define CLK_RTC 317 +#define CLK_TMU 318 +#define CLK_TMU_GPU 319 +#define CLK_PCLK66_GPIO 330 +#define CLK_ACLK200_FSYS2 350 +#define CLK_MMC0 351 +#define CLK_MMC1 352 +#define CLK_MMC2 353 +#define CLK_SROMC 354 +#define CLK_UFS 355 +#define CLK_ACLK200_FSYS 360 +#define CLK_TSI 361 +#define CLK_PDMA0 362 +#define CLK_PDMA1 363 +#define CLK_RTIC 364 +#define CLK_USBH20 365 +#define CLK_USBD300 366 +#define CLK_USBD301 367 +#define CLK_ACLK400_MSCL 380 +#define CLK_MSCL0 381 +#define CLK_MSCL1 382 +#define CLK_MSCL2 383 +#define CLK_SMMU_MSCL0 384 +#define CLK_SMMU_MSCL1 385 +#define CLK_SMMU_MSCL2 386 +#define CLK_ACLK333 400 +#define CLK_MFC 401 +#define CLK_SMMU_MFCL 402 +#define CLK_SMMU_MFCR 403 +#define CLK_ACLK200_DISP1 410 +#define CLK_DSIM1 411 +#define CLK_DP1 412 +#define CLK_HDMI 413 +#define CLK_ACLK300_DISP1 420 +#define CLK_FIMD1 421 +#define CLK_SMMU_FIMD1 422 +#define CLK_ACLK166 430 +#define CLK_MIXER 431 +#define CLK_ACLK266 440 +#define CLK_ROTATOR 441 +#define CLK_MDMA1 442 +#define CLK_SMMU_ROTATOR 443 +#define CLK_SMMU_MDMA1 444 +#define CLK_ACLK300_JPEG 450 +#define CLK_JPEG 451 +#define CLK_JPEG2 452 +#define CLK_SMMU_JPEG 453 +#define CLK_ACLK300_GSCL 460 +#define CLK_SMMU_GSCL0 461 +#define CLK_SMMU_GSCL1 462 +#define CLK_GSCL_WA 463 +#define CLK_GSCL_WB 464 +#define CLK_GSCL0 465 +#define CLK_GSCL1 466 +#define CLK_CLK_3AA 467 +#define CLK_ACLK266_G2D 470 +#define CLK_SSS 471 +#define CLK_SLIM_SSS 472 +#define CLK_MDMA0 473 +#define CLK_ACLK333_G2D 480 +#define CLK_G2D 481 +#define CLK_ACLK333_432_GSCL 490 +#define CLK_SMMU_3AA 491 +#define CLK_SMMU_FIMCL0 492 +#define CLK_SMMU_FIMCL1 493 +#define CLK_SMMU_FIMCL3 494 +#define CLK_FIMC_LITE3 495 +#define CLK_ACLK_G3D 500 +#define CLK_G3D 501 +#define CLK_SMMU_MIXER 502 + +/* mux clocks */ +#define CLK_MOUT_HDMI 640 + +/* divider clocks */ +#define CLK_DOUT_PIXEL 768 + +/* must be greater than maximal clock id */ +#define CLK_NR_CLKS 769 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h new file mode 100644 index 000000000000..70cd85077fa9 --- /dev/null +++ b/include/dt-bindings/clock/exynos5440.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Exynos5440 clock controller. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H + +#define CLK_XTAL 1 +#define CLK_ARM_CLK 2 +#define CLK_SPI_BAUD 16 +#define CLK_PB0_250 17 +#define CLK_PR0_250 18 +#define CLK_PR1_250 19 +#define CLK_B_250 20 +#define CLK_B_125 21 +#define CLK_B_200 22 +#define CLK_SATA 23 +#define CLK_USB 24 +#define CLK_GMAC0 25 +#define CLK_CS250 26 +#define CLK_PB0_250_O 27 +#define CLK_PR0_250_O 28 +#define CLK_PR1_250_O 29 +#define CLK_B_250_O 30 +#define CLK_B_125_O 31 +#define CLK_B_200_O 32 +#define CLK_SATA_O 33 +#define CLK_USB_O 34 +#define CLK_GMAC0_O 35 +#define CLK_CS250_O 36 + +/* must be greater than maximal clock id */ +#define CLK_NR_CLKS 37 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */ diff --git a/include/dt-bindings/clock/hi3620-clock.h b/include/dt-bindings/clock/hi3620-clock.h new file mode 100644 index 000000000000..6eaa6a45e110 --- /dev/null +++ b/include/dt-bindings/clock/hi3620-clock.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2012-2013 Hisilicon Limited. + * Copyright (c) 2012-2013 Linaro Limited. + * + * Author: Haojian Zhuang <haojian.zhuang@linaro.org> + * Xin Li <li.xin@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#ifndef __DTS_HI3620_CLOCK_H +#define __DTS_HI3620_CLOCK_H + +#define HI3620_NONE_CLOCK 0 + +/* fixed rate & fixed factor clocks */ +#define HI3620_OSC32K 1 +#define HI3620_OSC26M 2 +#define HI3620_PCLK 3 +#define HI3620_PLL_ARM0 4 +#define HI3620_PLL_ARM1 5 +#define HI3620_PLL_PERI 6 +#define HI3620_PLL_USB 7 +#define HI3620_PLL_HDMI 8 +#define HI3620_PLL_GPU 9 +#define HI3620_RCLK_TCXO 10 +#define HI3620_RCLK_CFGAXI 11 +#define HI3620_RCLK_PICO 12 + +/* mux clocks */ +#define HI3620_TIMER0_MUX 32 +#define HI3620_TIMER1_MUX 33 +#define HI3620_TIMER2_MUX 34 +#define HI3620_TIMER3_MUX 35 +#define HI3620_TIMER4_MUX 36 +#define HI3620_TIMER5_MUX 37 +#define HI3620_TIMER6_MUX 38 +#define HI3620_TIMER7_MUX 39 +#define HI3620_TIMER8_MUX 40 +#define HI3620_TIMER9_MUX 41 +#define HI3620_UART0_MUX 42 +#define HI3620_UART1_MUX 43 +#define HI3620_UART2_MUX 44 +#define HI3620_UART3_MUX 45 +#define HI3620_UART4_MUX 46 +#define HI3620_SPI0_MUX 47 +#define HI3620_SPI1_MUX 48 +#define HI3620_SPI2_MUX 49 +#define HI3620_SAXI_MUX 50 +#define HI3620_PWM0_MUX 51 +#define HI3620_PWM1_MUX 52 +#define HI3620_SD_MUX 53 +#define HI3620_MMC1_MUX 54 +#define HI3620_MMC1_MUX2 55 +#define HI3620_G2D_MUX 56 +#define HI3620_VENC_MUX 57 +#define HI3620_VDEC_MUX 58 +#define HI3620_VPP_MUX 59 +#define HI3620_EDC0_MUX 60 +#define HI3620_LDI0_MUX 61 +#define HI3620_EDC1_MUX 62 +#define HI3620_LDI1_MUX 63 +#define HI3620_RCLK_HSIC 64 +#define HI3620_MMC2_MUX 65 +#define HI3620_MMC3_MUX 66 + +/* divider clocks */ +#define HI3620_SHAREAXI_DIV 128 +#define HI3620_CFGAXI_DIV 129 +#define HI3620_SD_DIV 130 +#define HI3620_MMC1_DIV 131 +#define HI3620_HSIC_DIV 132 +#define HI3620_MMC2_DIV 133 +#define HI3620_MMC3_DIV 134 + +/* gate clocks */ +#define HI3620_TIMERCLK01 160 +#define HI3620_TIMER_RCLK01 161 +#define HI3620_TIMERCLK23 162 +#define HI3620_TIMER_RCLK23 163 +#define HI3620_TIMERCLK45 164 +#define HI3620_TIMERCLK67 165 +#define HI3620_TIMERCLK89 166 +#define HI3620_RTCCLK 167 +#define HI3620_KPC_CLK 168 +#define HI3620_GPIOCLK0 169 +#define HI3620_GPIOCLK1 170 +#define HI3620_GPIOCLK2 171 +#define HI3620_GPIOCLK3 172 +#define HI3620_GPIOCLK4 173 +#define HI3620_GPIOCLK5 174 +#define HI3620_GPIOCLK6 175 +#define HI3620_GPIOCLK7 176 +#define HI3620_GPIOCLK8 177 +#define HI3620_GPIOCLK9 178 +#define HI3620_GPIOCLK10 179 +#define HI3620_GPIOCLK11 180 +#define HI3620_GPIOCLK12 181 +#define HI3620_GPIOCLK13 182 +#define HI3620_GPIOCLK14 183 +#define HI3620_GPIOCLK15 184 +#define HI3620_GPIOCLK16 185 +#define HI3620_GPIOCLK17 186 +#define HI3620_GPIOCLK18 187 +#define HI3620_GPIOCLK19 188 +#define HI3620_GPIOCLK20 189 +#define HI3620_GPIOCLK21 190 +#define HI3620_DPHY0_CLK 191 +#define HI3620_DPHY1_CLK 192 +#define HI3620_DPHY2_CLK 193 +#define HI3620_USBPHY_CLK 194 +#define HI3620_ACP_CLK 195 +#define HI3620_PWMCLK0 196 +#define HI3620_PWMCLK1 197 +#define HI3620_UARTCLK0 198 +#define HI3620_UARTCLK1 199 +#define HI3620_UARTCLK2 200 +#define HI3620_UARTCLK3 201 +#define HI3620_UARTCLK4 202 +#define HI3620_SPICLK0 203 +#define HI3620_SPICLK1 204 +#define HI3620_SPICLK2 205 +#define HI3620_I2CCLK0 206 +#define HI3620_I2CCLK1 207 +#define HI3620_I2CCLK2 208 +#define HI3620_I2CCLK3 209 +#define HI3620_SCI_CLK 210 +#define HI3620_DDRC_PER_CLK 211 +#define HI3620_DMAC_CLK 212 +#define HI3620_USB2DVC_CLK 213 +#define HI3620_SD_CLK 214 +#define HI3620_MMC_CLK1 215 +#define HI3620_MMC_CLK2 216 +#define HI3620_MMC_CLK3 217 +#define HI3620_MCU_CLK 218 + +#define HI3620_NR_CLKS 219 + +#endif /* __DTS_HI3620_CLOCK_H */ diff --git a/include/dt-bindings/clock/qcom,gcc-msm8660.h b/include/dt-bindings/clock/qcom,gcc-msm8660.h new file mode 100644 index 000000000000..67665f6813dd --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8660.h @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H +#define _DT_BINDINGS_CLK_MSM_GCC_8660_H + +#define AFAB_CLK_SRC 0 +#define AFAB_CORE_CLK 1 +#define SCSS_A_CLK 2 +#define SCSS_H_CLK 3 +#define SCSS_XO_SRC_CLK 4 +#define AFAB_EBI1_CH0_A_CLK 5 +#define AFAB_EBI1_CH1_A_CLK 6 +#define AFAB_AXI_S0_FCLK 7 +#define AFAB_AXI_S1_FCLK 8 +#define AFAB_AXI_S2_FCLK 9 +#define AFAB_AXI_S3_FCLK 10 +#define AFAB_AXI_S4_FCLK 11 +#define SFAB_CORE_CLK 12 +#define SFAB_AXI_S0_FCLK 13 +#define SFAB_AXI_S1_FCLK 14 +#define SFAB_AXI_S2_FCLK 15 +#define SFAB_AXI_S3_FCLK 16 +#define SFAB_AXI_S4_FCLK 17 +#define SFAB_AHB_S0_FCLK 18 +#define SFAB_AHB_S1_FCLK 19 +#define SFAB_AHB_S2_FCLK 20 +#define SFAB_AHB_S3_FCLK 21 +#define SFAB_AHB_S4_FCLK 22 +#define SFAB_AHB_S5_FCLK 23 +#define SFAB_AHB_S6_FCLK 24 +#define SFAB_ADM0_M0_A_CLK 25 +#define SFAB_ADM0_M1_A_CLK 26 +#define SFAB_ADM0_M2_A_CLK 27 +#define ADM0_CLK 28 +#define ADM0_PBUS_CLK 29 +#define SFAB_ADM1_M0_A_CLK 30 +#define SFAB_ADM1_M1_A_CLK 31 +#define SFAB_ADM1_M2_A_CLK 32 +#define MMFAB_ADM1_M3_A_CLK 33 +#define ADM1_CLK 34 +#define ADM1_PBUS_CLK 35 +#define IMEM0_A_CLK 36 +#define MAHB0_CLK 37 +#define SFAB_LPASS_Q6_A_CLK 38 +#define SFAB_AFAB_M_A_CLK 39 +#define AFAB_SFAB_M0_A_CLK 40 +#define AFAB_SFAB_M1_A_CLK 41 +#define DFAB_CLK_SRC 42 +#define DFAB_CLK 43 +#define DFAB_CORE_CLK 44 +#define SFAB_DFAB_M_A_CLK 45 +#define DFAB_SFAB_M_A_CLK 46 +#define DFAB_SWAY0_H_CLK 47 +#define DFAB_SWAY1_H_CLK 48 +#define DFAB_ARB0_H_CLK 49 +#define DFAB_ARB1_H_CLK 50 +#define PPSS_H_CLK 51 +#define PPSS_PROC_CLK 52 +#define PPSS_TIMER0_CLK 53 +#define PPSS_TIMER1_CLK 54 +#define PMEM_A_CLK 55 +#define DMA_BAM_H_CLK 56 +#define SIC_H_CLK 57 +#define SPS_TIC_H_CLK 58 +#define SLIMBUS_H_CLK 59 +#define SLIMBUS_XO_SRC_CLK 60 +#define CFPB_2X_CLK_SRC 61 +#define CFPB_CLK 62 +#define CFPB0_H_CLK 63 +#define CFPB1_H_CLK 64 +#define CFPB2_H_CLK 65 +#define EBI2_2X_CLK 66 +#define EBI2_CLK 67 +#define SFAB_CFPB_M_H_CLK 68 +#define CFPB_MASTER_H_CLK 69 +#define SFAB_CFPB_S_HCLK 70 +#define CFPB_SPLITTER_H_CLK 71 +#define TSIF_H_CLK 72 +#define TSIF_INACTIVITY_TIMERS_CLK 73 +#define TSIF_REF_SRC 74 +#define TSIF_REF_CLK 75 +#define CE1_H_CLK 76 +#define CE2_H_CLK 77 +#define SFPB_H_CLK_SRC 78 +#define SFPB_H_CLK 79 +#define SFAB_SFPB_M_H_CLK 80 +#define SFAB_SFPB_S_H_CLK 81 +#define RPM_PROC_CLK 82 +#define RPM_BUS_H_CLK 83 +#define RPM_SLEEP_CLK 84 +#define RPM_TIMER_CLK 85 +#define MODEM_AHB1_H_CLK 86 +#define MODEM_AHB2_H_CLK 87 +#define RPM_MSG_RAM_H_CLK 88 +#define SC_H_CLK 89 +#define SC_A_CLK 90 +#define PMIC_ARB0_H_CLK 91 +#define PMIC_ARB1_H_CLK 92 +#define PMIC_SSBI2_SRC 93 +#define PMIC_SSBI2_CLK 94 +#define SDC1_H_CLK 95 +#define SDC2_H_CLK 96 +#define SDC3_H_CLK 97 +#define SDC4_H_CLK 98 +#define SDC5_H_CLK 99 +#define SDC1_SRC 100 +#define SDC2_SRC 101 +#define SDC3_SRC 102 +#define SDC4_SRC 103 +#define SDC5_SRC 104 +#define SDC1_CLK 105 +#define SDC2_CLK 106 +#define SDC3_CLK 107 +#define SDC4_CLK 108 +#define SDC5_CLK 109 +#define USB_HS1_H_CLK 110 +#define USB_HS1_XCVR_SRC 111 +#define USB_HS1_XCVR_CLK 112 +#define USB_HS2_H_CLK 113 +#define USB_HS2_XCVR_SRC 114 +#define USB_HS2_X |