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AgeCommit message (Expand)AuthorFilesLines
2018-07-25Linux 4.4.144v4.4.144Greg Kroah-Hartman1-1/+1
2018-07-25ubi: fastmap: Erase outdated anchor PEBs during attachSascha Hauer1-20/+57
2018-07-25ubi: Fix Fastmap's update_vol()Richard Weinberger1-0/+1
2018-07-25ubi: Fix races around ubi_refill_pools()Richard Weinberger4-14/+30
2018-07-25ubi: Be more paranoid while seaching for the most recent FastmapRichard Weinberger2-4/+27
2018-07-25ubi: Rework Fastmap attach base codeRichard Weinberger4-42/+162
2018-07-25ubi: Introduce vol_ignored()Richard Weinberger2-6/+33
2018-07-25clk: tegra: Fix PLL_U post divider and initial rate on Tegra30Lucas Stach1-5/+6
2018-07-25block: do not use interruptible wait anywhereAlan Jenkins1-7/+3
2018-07-25x86/cpu: Re-apply forced caps every time CPU caps are re-readAndy Lutomirski1-0/+7
2018-07-25x86/xen: Add call of speculative_store_bypass_ht_init() to PV pathsJuergen Gross1-0/+5
2018-07-25x86/bugs: Rename SSBD_NO to SSB_NOKonrad Rzeszutek Wilk2-2/+2
2018-07-25x86/speculation, KVM: Implement support for VIRT_SPEC_CTRL/LS_CFGThomas Gleixner2-0/+36
2018-07-25x86/bugs: Rework spec_ctrl base and mask logicThomas Gleixner1-7/+19
2018-07-25x86/bugs: Remove x86_spec_ctrl_set()Thomas Gleixner2-13/+2
2018-07-25x86/bugs: Expose x86_spec_ctrl_base directlyThomas Gleixner3-24/+6
2018-07-25x86/bugs: Unify x86_spec_ctrl_{set_guest, restore_host}Borislav Petkov2-49/+44
2018-07-25x86/speculation: Rework speculative_store_bypass_update()Thomas Gleixner3-4/+9
2018-07-25x86/speculation: Add virtualized speculative store bypass disable supportTom Lendacky4-2/+18
2018-07-25x86/bugs, KVM: Extend speculation control for VIRT_SPEC_CTRLThomas Gleixner2-5/+24
2018-07-25x86/speculation: Handle HT correctly on AMDThomas Gleixner3-6/+130
2018-07-25x86/cpufeatures: Add FEATURE_ZENThomas Gleixner2-0/+3
2018-07-25x86/cpu/AMD: Fix erratum 1076 (CPB bit)Borislav Petkov1-0/+11
2018-07-25x86/cpufeatures: Disentangle SSBD enumerationThomas Gleixner6-14/+15
2018-07-25x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumeration from IBRSThomas Gleixner4-9/+22
2018-07-25x86/speculation: Use synthetic bits for IBRS/IBPB/STIBPBorislav Petkov2-8/+18
2018-07-25x86/cpu: Make alternative_msr_write work for 32-bit codeJim Mattson1-2/+2
2018-07-25x86/bugs: Fix the parameters alignment and missing voidKonrad Rzeszutek Wilk1-2/+2
2018-07-25x86/bugs: Make cpu_show_common() staticJiri Kosina1-1/+1
2018-07-25x86/bugs: Fix __ssb_select_mitigation() return typeJiri Kosina1-1/+1
2018-07-25Documentation/spec_ctrl: Do some minor cleanupsBorislav Petkov1-12/+12
2018-07-25proc: Use underscores for SSBD in 'status'Konrad Rzeszutek Wilk1-1/+1
2018-07-25x86/bugs: Rename _RDS to _SSBDKonrad Rzeszutek Wilk9-47/+47
2018-07-25x86/speculation: Make "seccomp" the default mode for Speculative Store BypassKees Cook3-18/+41
2018-07-25seccomp: Move speculation migitation control to arch codeThomas Gleixner3-24/+22
2018-07-25seccomp: Add filter flag to opt-out of SSB mitigationKees Cook4-11/+93
2018-07-25seccomp: Use PR_SPEC_FORCE_DISABLEThomas Gleixner1-1/+1
2018-07-25prctl: Add force disable speculationThomas Gleixner5-23/+59
2018-07-25seccomp: Enable speculation flaw mitigationsKees Cook1-0/+17
2018-07-25proc: Provide details on speculation flaw mitigationsKees Cook1-0/+23
2018-07-25nospec: Allow getting/setting on non-current taskKees Cook3-17/+26
2018-07-25x86/speculation: Add prctl for Speculative Store Bypass mitigationThomas Gleixner3-11/+79
2018-07-25x86/process: Allow runtime control of Speculative Store BypassThomas Gleixner5-8/+66
2018-07-25x86/process: Optimize TIF_NOTSC switchThomas Gleixner2-18/+14
2018-07-25x86/process: Correct and optimize TIF_BLOCKSTEP switchKyle Huey2-5/+8
2018-07-25x86/process: Optimize TIF checks in __switch_to_xtra()Kyle Huey1-23/+31
2018-07-25prctl: Add speculation control prctlsThomas Gleixner4-0/+122
2018-07-25x86/speculation: Create spec-ctrl.h to avoid include hellThomas Gleixner6-18/+25
2018-07-25x86/bugs/AMD: Add support to disable RDS on Fam[15, 16, 17]h if requestedDavid Woodhouse5-1/+61
2018-07-25x86/bugs: Whitelist allowed SPEC_CTRL MSR valuesKonrad Rzeszutek Wilk1-2/+9
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