summaryrefslogtreecommitdiff
path: root/arch/riscv/kernel
AgeCommit message (Expand)AuthorFilesLines
2023-03-17riscv: Use READ_ONCE_NOCHECK in imprecise unwinding stack modeAlexandre Ghiti1-1/+1
2023-03-11RISC-V: time: initialize hrtimer based broadcast clock event deviceConor Dooley1-0/+3
2023-02-06exit: Add and use make_task_dead.Eric W. Biederman1-1/+1
2022-12-08RISC-V: vdso: Do not add missing symbols to version section in linker scriptNathan Chancellor2-0/+5
2022-11-25riscv: process: fix kernel info leakageJisheng Zhang1-0/+2
2022-10-29riscv: topology: fix default topology reportingConor Dooley1-1/+3
2022-10-26riscv: Allow PROT_WRITE-only mmap()Andrew Bresticker1-3/+0
2022-08-25RISC-V: Add fast call path of crash_kexec()Xianting Tian1-0/+4
2022-08-25riscv: mmap with PROT_WRITE but no PROT_READ is invalidCeleste Liu1-3/+2
2022-04-15riscv module: remove (NOLOAD)Fangrui Song1-3/+3
2022-04-15riscv: Fix fill_callchain return valueNikita Shubin1-1/+1
2022-03-16riscv: Fix auipc+jalr relocation range checksEmil Renner Berthing1-5/+16
2022-01-20perf: Protect perf_guest_cbs with RCUSean Christopherson1-2/+5
2021-09-26drivers: base: cacheinfo: Get rid of DEFINE_SMP_CALL_CACHE_FUNCTION()Thomas Gleixner1-5/+2
2021-05-22riscv: Workaround mcount name prior to clang-13Nathan Chancellor1-5/+5
2021-05-19RISC-V: Fix error code returned by riscv_hartid_to_cpuid()Anup Patel1-1/+1
2021-04-16riscv,entry: fix misaligned base for excp_vect_tableZihao Yu1-0/+1
2021-01-27riscv: Fix kernel time_init()Damien Le Moal1-0/+3
2020-11-18riscv: Set text_offset correctly for M-ModeSean Anderson1-0/+5
2020-10-01RISC-V: Take text_mutex in ftrace_init_nop()Palmer Dabbelt1-0/+19
2020-06-30RISC-V: Don't allow write+exec only page mapping request in mmapYash Shah1-0/+6
2020-06-03riscv: stacktrace: Fix undefined reference to `walk_stackframe'Kefeng Wang1-1/+1
2020-05-20riscv: fix vdso build with lldIlie Halip1-3/+3
2020-03-25riscv: avoid the PIC offset of static percpu data in module beyond 2G limitsVincent Chen1-0/+16
2020-02-05riscv: delete temporary filesIlie Halip1-1/+2
2020-01-14riscv: Implement copy_thread_tlsAmanieu d'Antras1-3/+3
2020-01-09riscv: ftrace: correct the condition logic in function graph tracerZong Li1-1/+1
2019-10-28riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley5-8/+8
2019-10-28riscv: fp: add missing __user pointer annotationsPaul Walmsley1-2/+2
2019-10-28riscv: add missing header file includesPaul Walmsley10-0/+12
2019-10-28riscv: mark some code and data as file-staticPaul Walmsley1-1/+1
2019-10-28riscv: add prototypes for assembly language functions from head.SPaul Walmsley3-0/+25
2019-10-25riscv: cleanup do_trap_breakChristoph Hellwig1-20/+6
2019-10-14riscv: remove the switch statement in do_trap_break()Vincent Chen1-11/+11
2019-10-09RISC-V: entry: Remove unneeded need_resched() loopValentin Schneider1-2/+1
2019-10-07riscv: Correct the handling of unexpected ebreak in do_trap_break()Vincent Chen1-3/+3
2019-10-07riscv: avoid sending a SIGTRAP to a user thread trapped in WARN()Vincent Chen1-1/+1
2019-10-07riscv: avoid kernel hangs when trapped in BUG()Vincent Chen1-3/+3
2019-10-01RISC-V: Clear load reservations while restoring hart contextsPalmer Dabbelt1-1/+20
2019-09-20riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen1-1/+5
2019-09-20RISC-V: Export kernel symbols for kvmAtish Patra2-0/+2
2019-09-20arch/riscv: disable excess harts before picking main boot hartXiang Wang1-3/+5
2019-09-16Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds8-35/+187
2019-09-16Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-0/+3
2019-09-13riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley1-2/+2
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig1-0/+1
2019-09-05riscv: optimize send_ipi_singleChristoph Hellwig1-1/+7
2019-09-05riscv: cleanup send_ipi_maskChristoph Hellwig1-9/+7
2019-09-05riscv: refactor the IPI codeChristoph Hellwig1-24/+31
2019-09-05riscv: Add support for perf registers samplingMao Han2-0/+45