linux.git - Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git

Age	Commit message (Expand)	Author	Files	Lines
2023-04-05	riscv: Bump COMMAND_LINE_SIZE value to 1024	Alexandre Ghiti	1	-0/+8
2023-03-11	RISC-V: time: initialize hrtimer based broadcast clock event device	Conor Dooley	1	-0/+3
2023-02-22	riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte	Guo Ren	1	-1/+3
2023-02-22	riscv: disable generation of unwind tables	Andreas Schwab	1	-0/+3
2023-02-06	exit: Add and use make_task_dead.	Eric W. Biederman	2	-2/+2
2023-01-18	riscv: uaccess: fix type of 0 variable on error in get_user()	Ben Dooks	1	-1/+1
2022-12-08	RISC-V: vdso: Do not add missing symbols to version section in linker script	Nathan Chancellor	2	-0/+5
2022-11-25	riscv: process: fix kernel info leakage	Jisheng Zhang	1	-0/+2
2022-10-26	riscv: fix build with binutils 2.38	Aurelien Jarno	1	-2/+9
2022-10-26	riscv: Allow PROT_WRITE-only mmap()	Andrew Bresticker	1	-3/+0
2022-08-25	RISC-V: Add fast call path of crash_kexec()	Xianting Tian	1	-0/+4
2022-08-25	riscv: mmap with PROT_WRITE but no PROT_READ is invalid	Celeste Liu	1	-3/+2
2022-07-29	riscv: add as-options for modules with assembly compontents	Ben Dooks	1	-0/+1
2022-06-25	RISC-V: fix barrier() use in <vdso/processor.h>	Randy Dunlap	1	-0/+2
2022-04-15	riscv module: remove (NOLOAD)	Fangrui Song	1	-3/+3
2022-03-16	riscv: Fix auipc+jalr relocation range checks	Emil Renner Berthing	1	-5/+16
2021-11-06	arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed	Arnd Bergmann	1	-0/+2
2021-09-26	drivers: base: cacheinfo: Get rid of DEFINE_SMP_CALL_CACHE_FUNCTION()	Thomas Gleixner	1	-5/+2
2021-05-22	riscv: Workaround mcount name prior to clang-13	Nathan Chancellor	2	-7/+17
2021-04-16	riscv,entry: fix misaligned base for excp_vect_table	Zihao Yu	1	-0/+1
2021-02-23	riscv: virt_addr_valid must check the address belongs to linear mapping	Alexandre Ghiti	1	-1/+4
2021-01-27	riscv: Fix kernel time_init()	Damien Le Moal	1	-0/+3
2020-11-05	riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO	Zong Li	1	-0/+3
2020-10-01	RISC-V: Take text_mutex in ftrace_init_nop()	Palmer Dabbelt	2	-0/+26
2020-07-29	RISC-V: Upgrade smp_mb__after_spinlock() to iorw,iorw	Palmer Dabbelt	1	-1/+9
2020-07-22	riscv: use 16KB kernel stack on 64-bit	Andreas Schwab	1	-0/+4
2020-06-30	RISC-V: Don't allow write+exec only page mapping request in mmap	Yash Shah	1	-0/+6
2020-06-30	riscv/atomic: Fix sign extension for RV64I	Nathan Huckleberry	1	-4/+4
2020-06-03	riscv: stacktrace: Fix undefined reference to `walk_stackframe'	Kefeng Wang	1	-1/+1
2020-05-27	riscv: set max_pfn to the PFN of the last page	Vincent Chen	1	-0/+2
2020-05-20	riscv: fix vdso build with lld	Ilie Halip	1	-3/+3
2020-03-25	riscv: avoid the PIC offset of static percpu data in module beyond 2G limits	Vincent Chen	1	-0/+16
2020-02-05	riscv: delete temporary files	Ilie Halip	1	-1/+2
2020-01-09	riscv: ftrace: correct the condition logic in function graph tracer	Zong Li	1	-1/+1
2019-12-01	RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap	Vincent Chen	1	-1/+1
2019-10-11	riscv: Avoid interrupts being erroneously enabled in handle_exception()	Vincent Chen	1	-1/+5
2019-09-16	riscv: remove unused variable in ftrace	David Abdurachmanov	1	-1/+0
2019-08-25	riscv: Make __fstate_clean() work correctly.	Vincent Chen	1	-1/+1
2019-07-14	riscv: Fix udelay in RV32.	Nick Hu	1	-1/+1
2019-06-25	riscv: mm: synchronize MMU after pte change	ShihPo Hung	1	-0/+13
2019-05-08	riscv: fix accessing 8-byte variable from RV32	Alan Kao	1	-1/+1
2019-04-17	riscv: Fix syscall_get_arguments() and syscall_set_arguments()	Dmitry V. Levin	1	-5/+7
2019-03-13	riscv: Adjust mmap base address at a third of task size	Alexandre Ghiti	1	-1/+1
2019-03-13	riscv: fixup max_low_pfn with PFN_DOWN.	Guo Ren	2	-2/+3
2019-02-20	riscv: Add pte bit to distinguish swap from invalid	Stefan O'Rear	2	-4/+10
2019-02-20	riscv: fix trace_sys_exit hook	David Abdurachmanov	1	-1/+1
2018-12-13	riscv: fix warning in arch/riscv/include/asm/module.h	David Abdurachmanov	1	-0/+1
2018-12-05	riscv/function_graph: Simplify with function_graph_enter()	Steven Rostedt (VMware)	1	-12/+2
2018-12-01	RISC-V: Silence some module warnings on 32-bit	Olof Johansson	1	-6/+6
2018-12-01	riscv: add missing vdso_install target	David Abdurachmanov	1	-0/+4