linux.git - Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git

Age	Commit message (Expand)	Author	Files	Lines
2024-09-21	clk: Switch back to struct platform_driver::remove()	Uwe Kleine-König	1	-1/+1
2024-09-21	Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-next	Stephen Boyd	14	-187/+1526
2024-09-02	clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT	Lad Prabhakar	2	-0/+88
2024-09-02	clk: renesas: rzv2h: Add support for dynamic switching divider clocks	Lad Prabhakar	2	-3/+201
2024-09-02	clk: renesas: r9a08g045: Add clocks, resets and power domains for USB	Claudiu Beznea	1	-0/+17
2024-08-20	clk: renesas: r8a779h0: Add CANFD clock	Cong Dang	1	-0/+1
2024-08-20	clk: renesas: Add RZ/V2H(P) CPG driver	Lad Prabhakar	5	-0/+94
2024-08-02	clk: Use of_property_present()	Rob Herring (Arm)	1	-1/+1
2024-08-02	clk: renesas: Add family-specific clock driver for RZ/V2H(P)	Lad Prabhakar	4	-0/+838
2024-08-02	clk: renesas: r8a779h0: Add PWM clock	Cong Dang	1	-0/+1
2024-07-30	clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs	Geert Uytterhoeven	5	-28/+20
2024-07-30	clk: renesas: rcar-gen4: Remove unused fixed PLL clock types	Geert Uytterhoeven	2	-24/+0
2024-07-30	clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type	Geert Uytterhoeven	2	-10/+0
2024-07-30	clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs	Geert Uytterhoeven	1	-5/+5
2024-07-30	clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs	Geert Uytterhoeven	1	-7/+7
2024-07-30	clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs	Geert Uytterhoeven	1	-6/+6
2024-07-30	clk: renesas: r8a779a0: Use defines for PLL control registers	Geert Uytterhoeven	1	-4/+9
2024-07-30	clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs	Geert Uytterhoeven	2	-0/+44
2024-07-30	clk: renesas: rcar-gen4: Add support for fixed variable PLLs	Geert Uytterhoeven	2	-10/+26
2024-07-30	clk: renesas: rcar-gen4: Add support for variable fractional PLLs	Geert Uytterhoeven	2	-7/+18
2024-07-30	clk: renesas: rcar-gen4: Add support for fractional multiplication	Geert Uytterhoeven	1	-16/+55
2024-07-30	clk: renesas: rcar-gen4: Use defines for common CPG registers	Geert Uytterhoeven	5	-21/+27
2024-07-30	clk: renesas: rcar-gen4: Use FIELD_GET()	Geert Uytterhoeven	2	-5/+11
2024-07-30	clk: renesas: rcar-gen4: Clarify custom PLL clock support	Geert Uytterhoeven	1	-15/+17
2024-07-30	clk: renesas: rcar-gen4: Removed unused SSMODE_* definitions	Geert Uytterhoeven	1	-4/+0
2024-07-30	clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock regi...	Lad Prabhakar	1	-28/+17
2024-07-30	clk: renesas: rzg2l-cpg: Use devres API to register clocks	Lad Prabhakar	1	-6/+20
2024-07-30	clk: renesas: r8a779h0: Initial clock descriptions should be __initconst	Geert Uytterhoeven	1	-3/+3
2024-07-30	clk: renesas: r8a779g0: cpg_pll_configs should be __initconst	Geert Uytterhoeven	1	-1/+1
2024-07-30	clk: renesas: r8a779f0: cpg_pll_configs should be __initconst	Geert Uytterhoeven	1	-1/+1
2024-07-30	clk: renesas: r8a779a0: cpg_pll_configs should be __initconst	Geert Uytterhoeven	1	-1/+1
2024-07-30	clk: renesas: r9a08g045: Add DMA clocks and resets	Claudiu Beznea	1	-0/+3
2024-07-30	clk: renesas: r9a07g043: Add LCDC clock and reset entries	Biju Das	1	-0/+12
2024-07-30	clk: renesas: r8a779h0: Add PCIe clock	Yoshihiro Shimoda	1	-0/+1
2024-06-27	clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C	Claudiu Beznea	1	-0/+20
2024-06-27	clk: renesas: r8a779h0: Add Audio clocks	Kuninori Morimoto	1	-0/+2
2024-06-27	clk: renesas: r9a08g045: Add clock, reset and power domain support for the VB...	Claudiu Beznea	1	-0/+6
2024-06-24	clk: renesas: Drop "Renesas" from individual driver descriptions	Geert Uytterhoeven	1	-2/+2
2024-06-24	clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments	Geert Uytterhoeven	1	-3/+3
2024-06-11	clk: renesas: r8a779h0: Add VIN clocks	Niklas Söderlund	1	-0/+16
2024-06-07	clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock	Geert Uytterhoeven	1	-3/+1
2024-06-07	clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock	Geert Uytterhoeven	3	-5/+1
2024-06-07	clk: renesas: r8a77970: Use common cpg_lock	Geert Uytterhoeven	1	-4/+1
2024-06-03	clk: renesas: r8a779h0: Add CSI-2 clocks	Niklas Söderlund	1	-0/+2
2024-06-03	clk: renesas: r8a779h0: Add ISPCS clocks	Niklas Söderlund	1	-0/+2
2024-04-25	clk: renesas: r9a08g045: Add support for power domains	Claudiu Beznea	1	-0/+41
2024-04-25	clk: renesas: rzg2l: Extend power domain support	Claudiu Beznea	2	-14/+252
2024-04-25	clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT	Geert Uytterhoeven	3	-6/+0
2024-04-25	clk: renesas: r8a7740: Remove unused div4_clk.flags field	Christophe JAILLET	1	-13/+12
2024-04-23	clk: renesas: r9a07g043: Add clock and reset entry for PLIC	Lad Prabhakar	1	-0/+9