Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2021-10-20 | clk: socfpga: agilex: fix duplicate s2f_user0_clk | Dinh Nguyen | 1 | -9/+0 |
2021-09-18 | clk: socfpga: agilex: add the bypass register for s2f_usr0 clock | Dinh Nguyen | 1 | -1/+1 |
2021-09-18 | clk: socfpga: agilex: fix up s2f_user0_clk representation | Dinh Nguyen | 1 | -0/+9 |
2021-09-18 | clk: socfpga: agilex: fix the parents of the psi_ref_clk | Dinh Nguyen | 1 | -4/+4 |
2021-07-14 | clk: agilex/stratix10: fix bypass representation | Dinh Nguyen | 1 | -11/+46 |
2021-07-14 | clk: agilex/stratix10: remove noc_clk | Dinh Nguyen | 1 | -17/+15 |
2020-09-22 | clk: socfpga: agilex: Remove unused variable 'cntr_mux' | YueHaibing | 1 | -13/+0 |
2020-06-19 | clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk | Dinh Nguyen | 1 | -1/+1 |
2020-06-19 | clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk | Dinh Nguyen | 1 | -1/+5 |
2020-05-26 | clk: socfpga: agilex: add clock driver for the Agilex platform | Dinh Nguyen | 1 | -0/+454 |