linux.git - Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git

Age	Commit message (Expand)	Author	Files	Lines
2018-09-26	clk: tegra: bpmp: Don't crash when a clock fails to register	Mikko Perttunen	1	-3/+9
2018-09-26	clk: clk-fixed-factor: Clear OF_POPULATED flag in case of failure	Rajan Vaja	1	-1/+8
2018-09-26	clk: core: Potentially free connection id	Mikko Perttunen	1	-0/+3
2018-09-26	clk: imx6ul: fix missing of_node_put()	Nicholas Mc Guire	1	-0/+1
2018-09-15	clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399	Levin Du	1	-0/+1
2018-09-05	clk: rockchip: fix clk_i2sout parent selection bits on rk3399	Alberto Panizzo	1	-1/+1
2018-08-17	clk: sunxi-ng: Fix missing CLK_SET_RATE_PARENT in ccu-sun4i-a10.c	Alexander Syring	1	-1/+1
2018-07-03	clk: at91: PLL recalc_rate() now using cached MUL and DIV values	Marcin Ziemianowicz	1	-12/+1
2018-07-03	clk: renesas: cpg-mssr: Stop using printk format %pCr	Geert Uytterhoeven	1	-4/+5
2018-06-21	clk: imx6ull: use OSC clock during AXI rate change	Stefan Agner	1	-1/+1
2018-06-21	clk: honor CLK_MUX_ROUND_CLOSEST in generic clk mux	Jerome Brunet	2	-4/+13
2018-05-25	clk: samsung: exynos3250: Fix PLL rates	Andrzej Hajda	1	-2/+2
2018-05-25	clk: samsung: exynos5250: Fix PLL rates	Andrzej Hajda	1	-4/+4
2018-05-25	clk: samsung: exynos5433: Fix PLL rates	Andrzej Hajda	1	-6/+6
2018-05-25	clk: samsung: exynos5260: Fix PLL rates	Andrzej Hajda	1	-1/+1
2018-05-25	clk: samsung: exynos7: Fix PLL rates	Andrzej Hajda	1	-1/+1
2018-05-25	clk: samsung: s3c2410: Fix PLL rates	Andrzej Hajda	1	-8/+8
2018-05-25	clk: rockchip: Prevent calculating mmc phase if clock rate is zero	Shawn Lin	1	-0/+23
2018-05-25	clk: tegra: Fix pll_u rate configuration	Marcel Ziswiler	1	-0/+2
2018-05-25	clk: hisilicon: mark wdt_mux_p[] as const	Arnd Bergmann	1	-1/+1
2018-05-25	clk: Don't show the incorrect clock phase	Shawn Lin	1	-0/+3
2018-05-25	clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228	Shawn Lin	1	-1/+1
2018-04-24	clk: bcm2835: De-assert/assert PLL reset signal when appropriate	Boris Brezillon	1	-3/+5
2018-04-24	clk: mediatek: fix PWM clock source by adding a fixed-factor clock	Sean Wang	1	-7/+8
2018-04-24	clk: fix false-positive Wmaybe-uninitialized warning	Arnd Bergmann	1	-3/+3
2018-04-24	clk: mvebu: armada-38x: add support for missing clocks	Richard Genoud	1	-7/+7
2018-04-12	clk: sunxi-ng: a83t: Add M divider to TCON1 clock	Jernej Škrabec	1	-2/+2
2018-04-12	clk: divider: fix incorrect usage of container_of	Jerome Brunet	5	-8/+7
2018-04-12	clk: meson: mpll: use 64-bit maths in params_from_rate	Martin Blumenstingl	1	-1/+1
2018-03-28	clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops	Chen-Yu Tsai	1	-3/+3
2018-03-28	clk: bcm2835: Protect sections updating shared registers	Boris Brezillon	1	-0/+4
2018-03-28	clk: bcm2835: Fix ana->maskX definitions	Boris Brezillon	1	-4/+4
2018-03-24	clk: migrate the count of orphaned clocks at init	Jerome Brunet	1	-16/+21
2018-03-24	clk: si5351: Rename internal plls to avoid name collisions	Sergej Sawazki	1	-1/+1
2018-03-24	clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()	Lars-Peter Clausen	1	-5/+24
2018-03-24	clk: Don't touch hardware when reparenting during registration	Stephen Boyd	1	-2/+5
2018-03-24	clk: at91: pmc: Wait for clocks when resuming	Romain Izard	1	-8/+16
2018-03-19	clk: qcom: msm8916: fix mnd_width for codec_digcodec	Srinivas Kandagatla	1	-0/+1
2018-03-19	clk: meson: gxbb: fix wrong clock for SARADC/SANA	Yixun Lan	1	-2/+2
2017-12-29	clk: sunxi: sun9i-mmc: Implement reset callback for reset controls	Chen-Yu Tsai	1	-0/+12
2017-12-25	clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision	Chen-Yu Tsai	1	-1/+1
2017-12-25	clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider	Chen-Yu Tsai	1	-2/+2
2017-12-25	clk: sunxi-ng: nm: Check if requested rate is supported by fractional clock	Chen-Yu Tsai	1	-0/+3
2017-12-20	clk: tegra: Fix cclk_lp divisor register	Michał Mirosław	1	-1/+1
2017-12-20	clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()	Nicolin Chen	1	-2/+2
2017-12-20	clk: hi6220: mark clock cs_atb_syspll as critical	Leo Yan	1	-1/+1
2017-12-20	clk: imx6: refine hdmi_isfr's parent to make HDMI work on i.MX6 SoCs w/o VPU	Sébastien Szymanski	1	-1/+1
2017-12-20	clk: imx: imx7d: Fix parent clock for OCRAM_CLK	Adriana Reus	1	-1/+1
2017-12-20	clk: mediatek: add the option for determining PLL source clock	Chen Zhong	2	-1/+5
2017-12-14	clk: hi3660: fix incorrect uart3 clock freqency	Zhong Kaihua	1	-1/+1