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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2022-01-27clk: si5341: Fix clock HW provider cleanupRobert Hancock1-1/+1
2022-01-27clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBBMartin Blumenstingl1-3/+41
2022-01-27clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system en...Dillon Min1-4/+0
2022-01-27clk: imx8mn: Fix imx8mn_clko1_selsAdam Ford1-3/+3
2022-01-27clk: bcm-2835: Remove rounding up the dividersMaxime Ripard1-8/+3
2022-01-27clk: bcm-2835: Pick the closest clock rateMaxime Ripard1-1/+1
2021-12-22clk: Don't parent clks until the parent is fully registeredMike Tipton1-3/+12
2021-12-14clk: qcom: regmap-mux: fix parent clock lookupDmitry Baryshkov3-1/+15
2021-11-26clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clkDmitry Baryshkov1-15/+0
2021-11-26clk/ast2600: Fix soc revision for AHBJoel Stanley1-5/+7
2021-11-26clk: ingenic: Fix bugs with divided dividersPaul Cercueil1-3/+3
2021-11-26clk: imx: imx6ul: Move csi_sel mux to correct base registerStefan Riedmueller1-1/+1
2021-11-17clk: at91: check pmc node status before registering syscore opsClément Léger1-0/+5
2021-11-17clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling pathsChristophe JAILLET1-3/+11
2021-09-22clk: at91: clk-generated: Limit the requested rate to our rangeCodrin Ciubotariu1-0/+6
2021-09-22clk: at91: clk-generated: pass the id of changeable parent at registrationClaudiu Beznea5-35/+37
2021-09-22clk: at91: sam9x60: Don't use audio PLLCodrin Ciubotariu1-6/+3
2021-09-15clk: kirkwood: Fix a clocking boot regressionLinus Walleij1-0/+1
2021-08-12clk: fix leak on devm_clk_bulk_get_all() unwindBrian Norris1-1/+8
2021-08-12clk: stm32f4: fix post divisor setup for I2S/SAI PLLsDario Binacchi1-5/+5
2021-07-19clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko1-5/+4
2021-07-19clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto1-0/+1
2021-07-14clk: si5341: Update initialization magicRobert Hancock1-1/+3
2021-07-14clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock1-2/+13
2021-07-14clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea1-15/+29
2021-07-14clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea1-4/+2
2021-07-14clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea1-6/+6
2021-07-14clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet1-1/+1
2021-06-23clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940Tony Lindgren1-0/+1
2021-05-19clk: exynos7: Mark aclk_fsys1_200 as criticalPaweł Chmiel1-1/+6
2021-05-14clk: uniphier: Fix potential infinite loopColin Ian King1-2/+2
2021-05-14clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLEChen Hui1-0/+1
2021-05-14clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callbackQuanyang Wang1-6/+6
2021-05-14media: aspeed: fix clock handling logicJae Hyun Yoo1-2/+2
2021-05-14clk: mvebu: armada-37xx-periph: Fix workaround for switching from L1 to L0Pali Rohár1-6/+39
2021-05-14clk: mvebu: armada-37xx-periph: Fix switching CPU freq from 250 Mhz to 1 GHzPali Rohár1-5/+7
2021-05-14clk: mvebu: armada-37xx-periph: remove .set_parent method for CPU PM clockMarek Behún1-28/+0
2021-05-11clk: socfpga: arria10: Fix memory leak of socfpga_clk on error returnColin Ian King1-0/+1
2021-04-14clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski1-1/+1
2021-04-14clk: fix invalid usage of list cursor in unregisterLukasz Bartosik1-17/+13
2021-04-14clk: fix invalid usage of list cursor in registerLukasz Bartosik1-9/+8
2021-03-04clk: aspeed: Fix APLL calculate formula from ast2600-A2Ryan Chen1-10/+27
2021-03-04clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLsAngeloGioacchino Del Regno1-50/+50
2021-03-04clk: sunxi-ng: h6: Fix clock divider range on some clocksAndre Przywara1-4/+4
2021-03-04clk: sunxi-ng: h6: Fix CEC clockAndre Przywara1-1/+1
2021-03-04clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl1-2/+3
2021-03-04clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl1-1/+2
2021-03-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl1-1/+1
2021-02-17clk: sunxi-ng: mp: fix parent rate change flag checkJernej Skrabec1-1/+1
2021-01-27clk: tegra30: Add hda clock default rates to clock driverPeter Geis1-0/+2