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path: root/drivers/clk
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2024-08-02clk: renesas: r8a779h0: Add PWM clockCong Dang1-0/+1
2024-07-31clk: qcom: fold dispcc-sm8650 info dispcc-sm8550Dmitry Baryshkov4-1811/+24
2024-07-31clk: qcom: dispcc-sm8550: use rcg2_shared_ops for ESC RCGsDmitry Baryshkov1-2/+2
2024-07-31clk: qcom: dispcc-sm8650: Update the GDSC flagsDmitry Baryshkov1-2/+2
2024-07-31clk: qcom: dispcc-sm8550: make struct clk_init_data constDmitry Baryshkov1-80/+80
2024-07-31clk: qcom: dispcc-sm8550: use rcg2_ops for mdss_dptx1_aux_clk_srcDmitry Baryshkov1-1/+1
2024-07-31clk: qcom: dispcc-sm8550: fix several supposed typosDmitry Baryshkov1-2/+2
2024-07-31clk: qcom: Add camera clock controller driver for SM8150Satya Priya Kakitapalli3-0/+2169
2024-07-31clk: qcom: clk-alpha-pll: Add support for Regera PLL opsTaniya Das2-1/+36
2024-07-31clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLLSatya Priya Kakitapalli1-0/+16
2024-07-31clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabledSatya Priya Kakitapalli1-0/+3
2024-07-31clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate APISatya Priya Kakitapalli1-2/+2
2024-07-31clk: qcom: clk-alpha-pll: Fix the pll post div maskSatya Priya Kakitapalli1-1/+1
2024-07-31clk: qcom: gcc-sc8180x: Add missing USB MP resetsBjorn Andersson1-0/+4
2024-07-31clk: thead: fix dependency on clk_ignore_unusedDrew Fustini1-1/+1
2024-07-31clk: samsung: exynos850: Add TMU clockSam Protsenko1-1/+6
2024-07-30clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configsGeert Uytterhoeven5-28/+20
2024-07-30clk: renesas: rcar-gen4: Remove unused fixed PLL clock typesGeert Uytterhoeven2-24/+0
2024-07-30clk: renesas: rcar-gen4: Remove unused variable PLL2 clock typeGeert Uytterhoeven2-10/+0
2024-07-30clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLsGeert Uytterhoeven1-5/+5
2024-07-30clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLsGeert Uytterhoeven1-7/+7
2024-07-30clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLsGeert Uytterhoeven1-6/+6
2024-07-30clk: renesas: r8a779a0: Use defines for PLL control registersGeert Uytterhoeven1-4/+9
2024-07-30clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLsGeert Uytterhoeven2-0/+44
2024-07-30clk: renesas: rcar-gen4: Add support for fixed variable PLLsGeert Uytterhoeven2-10/+26
2024-07-30clk: renesas: rcar-gen4: Add support for variable fractional PLLsGeert Uytterhoeven2-7/+18
2024-07-30clk: renesas: rcar-gen4: Add support for fractional multiplicationGeert Uytterhoeven1-16/+55
2024-07-30clk: renesas: rcar-gen4: Use defines for common CPG registersGeert Uytterhoeven5-21/+27
2024-07-30clk: renesas: rcar-gen4: Use FIELD_GET()Geert Uytterhoeven2-5/+11
2024-07-30clk: renesas: rcar-gen4: Clarify custom PLL clock supportGeert Uytterhoeven1-15/+17
2024-07-30clk: renesas: rcar-gen4: Removed unused SSMODE_* definitionsGeert Uytterhoeven1-4/+0
2024-07-30clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock regi...Lad Prabhakar1-28/+17
2024-07-30clk: renesas: rzg2l-cpg: Use devres API to register clocksLad Prabhakar1-6/+20
2024-07-30clk: renesas: r8a779h0: Initial clock descriptions should be __initconstGeert Uytterhoeven1-3/+3
2024-07-30clk: renesas: r8a779g0: cpg_pll_configs should be __initconstGeert Uytterhoeven1-1/+1
2024-07-30clk: renesas: r8a779f0: cpg_pll_configs should be __initconstGeert Uytterhoeven1-1/+1
2024-07-30clk: renesas: r8a779a0: cpg_pll_configs should be __initconstGeert Uytterhoeven1-1/+1
2024-07-30clk: renesas: r9a08g045: Add DMA clocks and resetsClaudiu Beznea1-0/+3
2024-07-30clk: renesas: r9a07g043: Add LCDC clock and reset entriesBiju Das1-0/+12
2024-07-30clk: renesas: r8a779h0: Add PCIe clockYoshihiro Shimoda1-0/+1
2024-07-29da8xx-cfgchip.c: replace of_node_put with __free improves cleanupDavid Hunter1-3/+1
2024-07-29clk: mediatek: reset: Remove unused mtk_register_reset_controller()AngeloGioacchino Del Regno2-69/+0
2024-07-29clk: mediatek: reset: Return regmap's error codeFei Shao1-2/+2
2024-07-29clk: Add KUnit tests for clks registered with struct clk_parent_dataStephen Boyd5-2/+495
2024-07-29clk: Add KUnit tests for clk fixed rate basic typeStephen Boyd6-0/+420
2024-07-29clk: Add test managed clk provider/consumer APIsStephen Boyd2-0/+212
2024-07-29clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228Jonas Karlman1-1/+1
2024-07-29clk: meson: introduce symbol namespace for amlogic clocksJerome Brunet25-25/+49
2024-07-29clk: meson: axg-audio: add sm1 earcrx clocksJerome Brunet2-1/+33
2024-07-29clk: meson: axg-audio: setup regmap max_register based on the SoCJerome Brunet1-2/+6