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path: root/drivers/cxl/core.c
AgeCommit message (Expand)AuthorFilesLines
2021-08-06cxl: Move cxl_core to new directoryBen Widawsky1-1067/+0
2021-06-15cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams1-0/+86
2021-06-15cxl/pmem: Add initial infrastructure for pmem supportDan Williams1-0/+121
2021-06-15cxl/core: Add cxl-bus driver infrastructureDan Williams1-0/+73
2021-06-12cxl/component_regs: Fix offsetBen Widawsky1-1/+1
2021-06-12cxl/hdm: Fix decoder count calculationBen Widawsky1-1/+1
2021-06-09cxl/acpi: Introduce cxl_decoder objectsDan Williams1-0/+265
2021-06-09cxl/acpi: Add downstream port data to cxl_port instancesDan Williams1-3/+104
2021-06-09cxl/acpi: Introduce the root of a cxl_port topologyDan Williams1-0/+160
2021-06-05cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *'Dan Williams1-7/+8
2021-06-05cxl/pci: Add HDM decoder capabilitiesBen Widawsky1-0/+92
2021-06-05cxl/pci: Reserve individual register block regionsIra Weiny1-4/+32
2021-06-05cxl/pci: Map registers based on capabilitiesIra Weiny1-12/+62
2021-05-26cxl/mem: Demarcate vendor specific capability IDsBen Widawsky1-1/+4
2021-05-14cxl/core: Refactor CXL register lookup for bridge reuseDan Williams1-0/+57
2021-05-14cxl/core: Rename bus.c to core.cDan Williams1-0/+30
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