summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/include/asic_reg
AgeCommit message (Expand)AuthorFilesLines
2019-06-22drm/amd/display: Create DWB resource for DCN2Charlene Liu2-0/+20
2019-06-20drm/amdgpu: add SMUIO 11.0 register headersHawking Zhang2-0/+1012
2019-06-20drm/amdgpu: add OSS 5.0 register headersHawking Zhang2-0/+1658
2019-06-20drm/amdgpu: add MMHUB 2.0 register headersHawking Zhang3-0/+10293
2019-06-20drm/amdgpu: add GC 10.1 register headers (v4)Hawking Zhang3-0/+61330
2019-06-20drm/amdgpu: add VCN 2.0 register headersHawking Zhang2-0/+4823
2019-06-20drm/amdgpu: add NBIO 2.3 register headersHawking Zhang3-0/+153523
2019-06-20drm/amdgpu: add MP 11.0 register headersHawking Zhang1-0/+429
2019-06-20drm/amdgpu: add HDP 5.0 register headersHawking Zhang2-0/+876
2019-06-20drm/amdgpu: add DCN 2.0 register headersHawking Zhang2-0/+85539
2019-06-20drm/amdgpu: add CLK 11.0 register headersHawking Zhang2-0/+71
2019-06-20drm/amdgpu: add ATHUB 2.0 register headersHawking Zhang3-0/+3050
2019-05-24drm/amdgpu: add df perfmon regs and funcs for xgmiJonathan Kim1-0/+18
2019-05-24drm/amdgpu: add EDC counter registerJames Zhu1-0/+31
2019-05-24drm/amdgpu: Add replay counter defines to NBIO headersKent Russell3-0/+9
2019-04-23drm/amd/include: Add HUBPREQ_DEBUG register offsetsLeo Li1-0/+8
2019-03-19drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headersTom St Denis2-0/+7
2019-01-25drm/amdgpu: update THM IP register header to support BACOJim Qu1-0/+3
2019-01-25drm/amdgpu: update NBIO v7.4 to support BACOJim Qu2-0/+5
2019-01-14drm/amdgpu: update nbio v6.1 register/master to support BACOJim Qu2-0/+6
2019-01-14drm/amdgpu: Add NBIO SMN headers v2Kent Russell3-0/+165
2018-12-05drm/amd/include: Add mmhub 9.4 reg offsets and shift-maskLeo Li2-0/+67
2018-10-12drm/amdgpu/vcn:Add new register offset/mask for VCNJames Zhu2-0/+32
2018-10-10drm/amdgpu: add CP_DEBUG register definition for GC9.0Tao Zhou1-0/+2
2018-10-09drm/amd/powerplay/vega20: enable fan RPM and pwm settings V2Evan Quan2-0/+22
2018-10-09drm/amd/powerplay/vega20: tell the correct gfx voltage V2Evan Quan2-0/+6
2018-09-26drm/amdgpu:Add new register offset/mask to support VCN DPG modeJames Zhu2-0/+33
2018-09-10drm/amd/include: update the bitfield define for PF_MAX_REGIONShaoyun Liu1-2/+2
2018-08-27drm/amdgpu/include: Add mp 11.0 header files. (v2)Feifei Xu2-0/+892
2018-08-27drm/amdgpu/include: add thm 11.0.2 headersEvan Quan2-0/+123
2018-08-27drm/amdgpu/include: Add sdma0/1 4.2 register headerfiles. (v3)Feifei Xu4-0/+8026
2018-08-27drm/amdgpu/include: Add nbio 7.4 header files (v4)Feifei Xu2-0/+53063
2018-08-27drm/amdgpu: add system interrupt mask for jrbcBoyuan Zhang1-0/+2
2018-08-27drm/amdgpu: add system interrupt register offset headerBoyuan Zhang1-0/+2
2018-06-15drm/amdgpu: add more jpeg register offset headersBoyuan Zhang1-0/+20
2018-06-13drm/amd/include: Update df 3.6 mask and shift definitionShaoyun Liu1-4/+4
2018-05-23drm/amdgpu: add new DF 1.7 register defsAlex Deucher2-0/+8
2018-05-18drm/amdgpu: add df 3.6 headersAlex Deucher3-0/+107
2018-05-17drm/amd: Add dce-12.1 gpio aux registers (v2)Roman Li2-0/+164
2018-04-11drm/amdgpu: add df v1_7 header filesHawking Zhang3-0/+107
2018-04-11drm/amdgpu: Add CM_TEST_DEBUG regs for DCNHarry Wentland2-3/+24
2018-03-21drm/amd/include: Add ip header files for vega12.Feifei Xu6-0/+52499
2018-03-07drm/amd/amdgpu: re-add missing GC 9.1 and SDMA0 4.1 sh_mask header filesTom St Denis2-0/+32808
2018-02-19drm/amd/display: Adding missing TMZ sh/mask entries for DCN1 SURFACE_CONTROLHarry Wentland1-0/+14
2018-02-19drm/amd/pp: Export registers for read vddc on VI/Vega10Rex Zhu4-2/+11
2017-12-13drm/amdgpu: remove some old gc 9.x registersAlex Deucher4-80/+0
2017-12-06drm/amd/include:cleanup raven1 vcn header files.Feifei Xu3-202/+0
2017-12-06drm/amd/include:cleanup raven1 thm header files.Feifei Xu3-0/+0
2017-12-06drm/amd/include:cleanup raven1 nbio header files.Feifei Xu3-0/+0
2017-12-06drm/amd/include:cleanup raven1 mp header files.Feifei Xu3-0/+0
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-27 05:44:01 +0000