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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
AgeCommit message (Expand)AuthorFilesLines
2024-06-28drm/i915/mtl: Skip PLL state verification in TBT modeImre Deak1-0/+1
2024-05-30drm/i915/display: Add compare config for MTL+ platformsMika Kahola1-0/+1
2024-04-17drm/i915: Suck snps/cx0 PLL states into dpll_hw_stateVille Syrjälä1-0/+39
2024-04-17drm/i915: Unionize dpll_hw_stateVille Syrjälä1-5/+7
2024-04-17drm/i915: Carve up struct intel_dpll_hw_stateVille Syrjälä1-13/+20
2024-04-17drm/i915: Rename PLL hw_state variables/argumentsVille Syrjälä1-3/+3
2024-03-15drm/i915: Convert intel_dpll_dump_hw_state() to drm_printerVille Syrjälä1-0/+2
2024-02-15drm/i915: Add PLL .compare_hw_state() vfuncVille Syrjälä1-0/+3
2024-01-26drm/i915: Convert PLL flags to booleansVille Syrjälä1-11/+13
2024-01-26drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLsVille Syrjälä1-0/+4
2023-10-31drm/i915: Abstract the extra JSL/EHL DPLL4 power domain betterVille Syrjälä1-0/+6
2023-10-06drm/i915: Simplify DPLL state checker calling conventionVille Syrjälä1-4/+3
2023-10-06drm/i915: Constify the crtc states in the DPLL checkerVille Syrjälä1-2/+2
2023-10-04drm/i915: s/dev_priv/i915/ in the shared_dpll codeVille Syrjälä1-7/+7
2023-10-04drm/i915: Introduce for_each_shared_dpll()Ville Syrjälä1-0/+4
2023-10-04drm/i915: Stop requiring PLL index == PLL IDVille Syrjälä1-2/+6
2023-08-18drm/i915: Move abs_diff() to math.hAndy Shevchenko1-7/+0
2023-05-16drm/i915: Make the CRTC state consistent during sanitize-disablingImre Deak1-0/+3
2022-09-26drm/i915: Nuke intel_get_shared_dpll_id()Ville Syrjälä1-3/+0
2022-06-17drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.cJani Nikula1-0/+5
2022-05-31drm/i915: Split shared dpll .get_dplls() into compute and get phasesVille Syrjälä1-0/+3
2022-04-25drm/i915: Pass dev_priv to intel_shared_dpll_init()Ville Syrjälä1-2/+1
2022-04-25drm/i915: Make .get_dplls() return intVille Syrjälä1-3/+3
2022-02-18drm/i915/display/tgl+: Implement new PLL programming stepJosé Roberto de Souza1-0/+3
2022-01-19drm/i915/dpll: make intel_shared_dpll_funcs internal to intel_dpll_mgr.cJani Nikula1-45/+1
2021-11-19drm/i915: drop intel_display.h include from intel_dpll_mgr.hJani Nikula1-1/+1
2021-08-25drm/i915: Nuke intel_prepare_shared_dpll()Ville Syrjälä1-11/+0
2021-07-30drm/i915: replace random CNL commentsLucas De Marchi1-2/+1
2021-03-08drm/i915: Use pipes instead crtc indices in PLL state trackingVille Syrjälä1-4/+4
2021-03-08drm/i915: Do intel_dpll_readout_hw_state() after encoder readoutVille Syrjälä1-0/+1
2020-11-16drm/i915: Use actual readout results for .get_freq()Ville Syrjälä1-3/+5
2020-11-16drm/i915: Introduce intel_dpll_get_hw_state()Ville Syrjälä1-0/+3
2020-10-15drm/i915/dg1: Add DPLL macros for DG1Aditya Swarup1-0/+17
2020-03-09drm/i915: Fix documentation for intel_dpll_get_freq()Imre Deak1-0/+6
2020-03-02drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculationImre Deak1-3/+5
2020-03-02drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.cImre Deak1-0/+2
2020-03-02drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.cImre Deak1-0/+2
2019-10-25drm/i915/tgl: Fix doc not corresponding to codeAnna Karas1-2/+2
2019-10-25drm/i915: Describe structure member in documentationAnna Karas1-0/+5
2019-07-11drm/i915/tgl: Add new pll idsVandita Kulkarni1-5/+18
2019-07-11drm/i915: Polish intel_shared_dpll_swap_state()Ville Syrjälä1-2/+1
2019-07-05drm/i915/ehl: Add support for DPLL4 (v10)Vivek Kasireddy1-0/+6
2019-07-01drm/i915: Keep the TypeC port mode fixed when the port is activeImre Deak1-0/+3
2019-07-01drm/i915/icl: Reserve all required PLLs for TypeC portsImre Deak1-0/+9
2019-07-01drm/i915: Sanitize the shared DPLL reserve/release interfaceImre Deak1-6/+7
2019-06-17drm/i915: move modesetting core code under display/Jani Nikula1-0/+351
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