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path: root/drivers/gpu/drm/i915/display/intel_snps_phy.c
AgeCommit message (Expand)AuthorFilesLines
2024-04-17drm/i915: Suck snps/cx0 PLL states into dpll_hw_stateVille Syrjälä1-3/+3
2024-03-21drm/i915/display: use intel_encoder_is/to_* functionsJani Nikula1-6/+6
2024-03-21drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state()Jani Nikula1-2/+4
2023-12-04drm/i915/display: Don't use "proxy" headersAndy Shevchenko1-1/+1
2023-10-16drm/i915/display: Clean up zero initializersVille Syrjälä1-1/+1
2023-10-07drm/i915: Simplify snps/c10x DPLL state checker calling convetionVille Syrjälä1-2/+3
2023-10-07drm/i915: Constify the snps/c10x PLL state checkersVille Syrjälä1-2/+2
2023-05-15drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula1-1/+1
2023-04-15drm/i915: Make intel_{mpllb,c10pll}_state_verify() saferVille Syrjälä1-0/+5
2023-02-24drm/i915/dg2: Add HDMI pixel clock frequencies 267.30 and 319.89 MHzAnkit Nautiyal1-0/+62
2023-01-18drm/i915: move snps_phy_failed_calibration to display sub-struct under snpsJani Nikula1-1/+1
2022-12-08drm/i915/snps: switch to intel_de_* register accessors in display codeJani Nikula1-8/+7
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula1-0/+1
2022-08-24drm/i915/dg2: Add additional HDMI pixel clock frequenciesTaylor, Clinton A1-0/+1116
2022-06-17drm/i915/mpllb: move mpllb state check to intel_snps_phy.cJani Nikula1-0/+43
2022-05-31drm/i915: Require an exact DP link freq match for the DG2 PLLVille Syrjälä1-1/+1
2022-05-25drm/i915/dg2: Support 4k@30 on HDMIVandita Kulkarni1-0/+32
2022-02-24drm/i915/dg2: Skip output init on PHY calibration failureMatt Roper1-2/+6
2022-02-18drm/i915/dg2: Drop 38.4 MHz MPLLB tablesMatt Roper1-207/+1
2022-02-18drm/i915: Fix for PHY_MISC_TC1 offsetJouni Högander1-1/+1
2022-02-17drm/i915/dg2: Print PHY name properly on calibration errorMatt Roper1-1/+1
2022-01-24drm/i915/snps: convert to drm device based loggingJani Nikula1-14/+15
2022-01-11drm/i915: Move SNPS PHY registers to their own headerMatt Roper1-0/+1
2021-12-07drm/i915/snps: use div32 version of MPLLB word clock for UHBRJani Nikula1-0/+2
2021-11-03drm/i915: Query the vswing levels per-lane for snps phyVille Syrjälä1-1/+1
2021-10-14drm/i915: Remove pointless extra namespace from dkl/snps buf trans structsVille Syrjälä1-3/+3
2021-10-04drm/i915: Pass the lane to intel_ddi_level()Ville Syrjälä1-1/+1
2021-10-04drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level()Ville Syrjälä1-2/+0
2021-10-04drm/i915: Nuke useless .set_signal_levels() wrappersVille Syrjälä1-3/+4
2021-09-30drm/i915: s/ddi_translations/trans/Ville Syrjälä1-6/+6
2021-08-30drm/i915/dg2: UHBR tables added for pll programmingAnimesh Manna1-0/+147
2021-08-26drm/i915/snps: constify struct intel_mpllb_state arrays harderJani Nikula1-7/+7
2021-08-13drm/i915/dg2: use existing mechanisms for SNPS PHY translationsJani Nikula1-44/+17
2021-07-29drm/i915/dg2: Update lane disable power state during PSRGwan-gyeong Mun1-0/+14
2021-07-29drm/i915/dg2: Wait for SNPS PHY calibration during display initMatt Roper1-0/+15
2021-07-29drm/i915/dg2: Add vswing programming for SNPS physMatt Roper1-0/+54
2021-07-29drm/i915/dg2: Add MPLLB programming for HDMIMatt Roper1-12/+274
2021-07-29drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper1-0/+517
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