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path: root/drivers/gpu/drm/i915/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2018-07-13drm/i915: Nuke dev_priv->irq_port[]Ville Syrjälä1-1/+0
2018-07-13drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.Clint Taylor1-2/+11
2018-07-06drm/i915/ddi: Simplify get_encoder_power_domains()Imre Deak1-12/+7
2018-07-05drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva1-0/+1
2018-06-26drm/i915/ddi: Get AUX power domain for DP main link tooImre Deak1-4/+50
2018-06-15drm/i915/icl: implement DVFS for ICLPaulo Zanoni1-0/+2
2018-06-14drm/i915/icl: start adding the TBT pllPaulo Zanoni1-0/+16
2018-06-14drm/i915/ddi: Set HDMI infoframes with pipe clocks enabledImre Deak1-5/+5
2018-06-14drm/i915/ddi: Push pipe clock enabling to encodersImre Deak1-0/+8
2018-06-12drm/i915/icl: Add DDI HDMI level selection for ICLManasi Navare1-1/+8
2018-06-01drm/i915/icl: Calculate link clock using the new registersArkadiusz Hiler1-2/+7
2018-06-01drm/i915/icl: Get DDI clock for ICL based on PLLs.Manasi Navare1-0/+26
2018-06-01drm/i915/icl: fix icl_unmap/map_plls_to_portsMahesh Kumar1-2/+4
2018-05-23drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi codeVille Syrjälä1-29/+0
2018-05-18drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+Ville Syrjälä1-0/+20
2018-05-07drm/i915/icl: add basic support for the ICL clocksPaulo Zanoni1-4/+94
2018-04-30drm/i915/icl: Fix the DP Max Voltage for ICLManasi Navare1-1/+7
2018-04-30drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDIManasi Navare1-3/+188
2018-04-07drm/i915/dp: Send DPCD ON for MST before phy_upLyude Paul1-2/+6
2018-03-27drm/i915: use id from intel_shared_dpll.infoLucas De Marchi1-4/+4
2018-03-23drm/i915/icl: Add Voltage swing table for MG PHY DDI BufferManasi Navare1-0/+20
2018-03-23drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.Manasi Navare1-0/+99
2018-03-23drm/i915: Don't spew errors when resetting HDMI scrambling/bit clock ratio failsVille Syrjälä1-7/+12
2018-03-19drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.Dhinakaran Pandiyan1-5/+2
2018-03-09drm/i915/icl: do not save DDI A/E sharing bit for ICLJani Nikula1-3/+6
2018-03-06drm/i915: Track whether the DP link is trained or notVille Syrjälä1-0/+2
2018-03-06drm/i915: Move SST DP link retraining into the ->post_hotplug() hookVille Syrjälä1-5/+5
2018-03-06drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPDVille Syrjälä1-0/+146
2018-03-05drm/i915/icl: remove port A/E lane sharing limitation.Mahesh Kumar1-46/+39
2018-03-01Merge tag 'drm-intel-next-2018-02-21' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-1/+1
2018-02-16Merge tag 'topic/hdcp-2018-02-13' of git://anongit.freedesktop.org/drm/drm-mi...Dave Airlie1-0/+36
2018-02-09drm/i915: Use INTEL_GEN everywhereTvrtko Ursulin1-1/+1
2018-01-30drm/i915/cnl: Enable DDI-F on Cannonlake.Rodrigo Vivi1-0/+4
2018-01-24drm/i915: Implement display w/a #1143Ville Syrjälä1-0/+42
2018-01-08drm/i915: Implement HDCP for HDMISean Paul1-0/+29
2018-01-08drm/i915: Add HDCP framework + base implementationSean Paul1-0/+7
2017-12-19drm/i915: Fix indentation for intel_ddi_clk_selectChris Wilson1-2/+2
2017-12-18drm/i915: Protect DDI port to DPLL map from theoretical race.Rodrigo Vivi1-0/+4
2017-12-01drm/i915/cnl: Mask previous DDI - PLL mappingJames Ausmus1-0/+1
2017-12-01drm/i915: Fix has_audio readout for DDI AVille Syrjälä1-10/+10
2017-11-14drm/i915: Generalize transcoder loopingMika Kahola1-4/+6
2017-11-09drm/i915: Nuke intel_digital_port->portVille Syrjälä1-7/+6
2017-10-31drm/i915: Pass around crtc and connector states for audioVille Syrjälä1-2/+4
2017-10-30drm/i915: Use intel_ddi_get_config() for MSTVille Syrjälä1-3/+3
2017-10-30drm/i915: Pass a crtc state to ddi post_disable from MST codeVille Syrjälä1-11/+26
2017-10-30drm/i915: Eliminate pll->state usage from bxt_calc_pll_link()Ville Syrjälä1-12/+5
2017-10-30drm/i915: Nuke intel_ddi_get_encoder_port()Ville Syrjälä1-33/+17
2017-10-30drm/i915: Stop frobbing with DDI encoder->typeVille Syrjälä1-8/+24
2017-10-30drm/i915: Populate output_types from .get_config()Ville Syrjälä1-0/+11
2017-10-27drm/i915: Fix BXT lane latency optimal setting with MSTVille Syrjälä1-2/+1
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