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path: root/drivers/gpu/drm/msm/dsi/phy
AgeCommit message (Expand)AuthorFilesLines
2024-09-02drm/msm/dsi: correct programming sequence for SM8350 / SM8450Dmitry Baryshkov1-1/+11
2024-06-25drm/msm/dsi: Add phy configuration for MSM8937Daniil Titov3-0/+21
2024-06-23drm/msm/dsi: Remove dsi_phy_write_[un]delay()Konrad Dybcio3-33/+54
2024-06-23drm/msm/dsi: Remove dsi_phy_read/write()Konrad Dybcio7-703/+645
2024-04-22drm/msm: Drop msm_read/writelKonrad Dybcio1-4/+4
2023-12-10Merge remote-tracking branch 'drm-misc/drm-misc-next' into msm-nextRob Clark1-1/+1
2023-12-05drm/msm: dsi: add support for DSI-PHY on SM8650Neil Armstrong3-0/+30
2023-12-03drm/msm/dsi: Enable runtime PMKonrad Dybcio1-0/+4
2023-12-03drm/msm/dsi: Use pm_runtime_resume_and_get to prevent refcnt leaksKonrad Dybcio1-1/+3
2023-11-16drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphyJonathan Marek1-1/+1
2023-07-27drm/msm/dsi: Reuse QCM2290 14nm DSI PHY configuration for SM6125Marijn Suijten1-0/+2
2023-07-27drm/msm/dsi: Drop unused regulators from QCM2290 14nm DSI PHY configMarijn Suijten1-2/+0
2023-06-04drm/msm/dsi: Add phy configuration for MSM8226Luca Weiss3-1/+101
2023-05-21drm/msm/dsi: don't allow enabling 14nm VCO with unprogrammed rateDmitry Baryshkov1-0/+3
2023-01-22drm/msm/dsi: correct byte intf clock rate for 14nm DSI PHYDmitry Baryshkov1-0/+4
2023-01-22drm/msm/dsi: Add phy configuration for SM6375Konrad Dybcio3-0/+23
2023-01-22drm/msm/dsi: add support for DSI-PHY on SM8550Neil Armstrong3-14/+77
2023-01-22drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450Dmitry Baryshkov3-10/+115
2023-01-09drm/msm/dsi/phy: rework register setting for 7nm PHYDmitry Baryshkov1-13/+13
2022-11-04drm/msm/dsi: Add phy configuration for QCM2290Loic Poulain3-0/+20
2022-09-18drm/msm/dsi: Improve dsi_phy_driver_probe() probe error handlingDouglas Anderson1-47/+27
2022-09-18drm/msm/dsi: Take advantage of devm_regulator_bulk_get_const()Douglas Anderson8-112/+68
2022-09-18drm/msm/dsi: Use the new regulator bulk feature to specify the loadDouglas Anderson1-10/+3
2022-09-18drm/msm/dsi: Don't set a load before disabling a regulatorDouglas Anderson7-61/+19
2022-09-18drm/msm/dsi_phy_7nm: Replace parent names with clk_hw pointersMarijn Suijten1-36/+34
2022-09-18drm/msm/dsi_phy_10nm: Replace parent names with clk_hw pointersMarijn Suijten1-43/+36
2022-09-18drm/msm/dsi_phy_14nm: Replace parent names with clk_hw pointersMarijn Suijten1-21/+19
2022-09-18drm/msm/dsi_phy_28nm: Replace parent names with clk_hw pointersMarijn Suijten1-27/+23
2022-09-18drm/msm/dsi_phy_28nm_8960: Replace parent names with clk_hw pointersMarijn Suijten1-7/+8
2022-09-18drm/msm/dsi/phy: Replace hardcoded char-array length with sizeof()Marijn Suijten5-60/+60
2022-09-18drm/msm/dsi_phy_28nm_8960: Use stack memory for temporary clock namesMarijn Suijten1-13/+1
2022-09-18drm/msm/dsi/phy: Reindent and reflow multiline function callsMarijn Suijten5-164/+161
2022-09-18drm/msm/dsi: fix the inconsistent indentingsunliming1-1/+1
2022-05-07drm/msm/dsi: pll_7nm: remove unsupported dividers for DSI pixel clockDmitry Baryshkov1-6/+4
2022-05-07drm/msm/dsi: fix address for second DSI PHY on SDM660Dmitry Baryshkov1-1/+1
2022-02-19Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-d...Dmitry Baryshkov7-19/+151
2022-02-18drm/msm/dsi/phy: fix 7nm v4.0 settings for C-PHY modeDmitry Baryshkov1-8/+14
2022-02-18drm/msm/dsi: Add 10nm dsi phy tuning configuration supportRajeev Nandan1-6/+112
2022-02-18drm/msm/dsi: Add dsi phy tuning configuration supportRajeev Nandan2-0/+10
2022-02-18drm/msm/dsi: Use "ref" fw clock instead of global name for VCO parentMarijn Suijten5-5/+15
2022-02-18drm/msm: drop dbgname argument from msm_ioremap*()Dmitry Baryshkov1-4/+4
2022-01-25drm/msm/dsi: invalid parameter check in msm_dsi_phy_enableJosé Expósito1-1/+3
2021-12-16drm/msm: Don't use autosuspend for displayRob Clark1-1/+1
2021-11-28drm/msm/dsi: stop setting clock parents manuallyDmitry Baryshkov1-11/+0
2021-10-15drm/msm/dsi: Add phy configuration for MSM8953Vladimir Lypak3-0/+24
2021-10-15drm/msm/dsi: Use division result from div_u64_rem in 7nm and 14nm PLLMarijn Suijten2-6/+2
2021-10-11drm/msm/dsi: dsi_phy_14nm: Take ready-bit into account in poll_for_readyMarijn Suijten1-15/+15
2021-10-11drm/msm/dsi/phy: fix clock names in 28nm_8960 phyDmitry Baryshkov1-2/+2
2021-08-10drm/msm/dsi: add continuous clock support for 7nm PHYDmitry Baryshkov3-0/+27
2021-08-07drm/msm/dsi: Fix DSI and DSI PHY regulator config from SDM660Konrad Dybcio1-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-14 07:11:40 +0000