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path: root/drivers/gpu/drm/msm
AgeCommit message (Expand)AuthorFilesLines
2026-03-19drm/msm/dpu: Correct the SA8775P intr_underrun/intr_underrun indexAbhinav Kumar1-2/+2
2026-03-19drm/msm: Fix dma_free_attrs() buffer sizeThomas Fourier1-1/+1
2026-03-19drm/msm/dsi: fix pclk rate calculation for bonded dsiPengyu Luo1-6/+23
2026-03-19drm/msm/dsi: fix hdisplay calculation when programming dsi registersPengyu Luo1-6/+8
2026-02-26drm/msm/dp: Avoid division by zero in msm_dp_ctrl_config_msa()Nathan Chancellor1-6/+18
2026-02-26drm/msm/dpu: program correct register for UBWC config on DPU 8.x+Dmitry Baryshkov1-6/+19
2026-02-26drm/msm/dpu: offset HBB values written to DPU by -13Dmitry Baryshkov1-4/+6
2026-02-26drm/msm/mdss: correct HBB programmed on UBWC 5.x and 6.x devicesDmitry Baryshkov1-1/+1
2026-02-26drm/msm/a2xx: fix pixel shader start on A225Dmitry Baryshkov1-1/+4
2026-02-26drm/msm/dsi_phy_14nm: convert from divider_round_rate() to divider_determine_...Brian Masney1-6/+1
2026-02-26drm/msm/dpu: fix CMD panels on DPU 1.x - 3.xDmitry Baryshkov1-3/+4
2026-02-26drm/msm/disp: set num_planes to 1 for interleaved YUV formatsDmitry Baryshkov1-4/+4
2026-02-26drm/msm/dp: Update msm_dp_controller IDs for sa8775pMani Chandana Ballary Kuntumalla1-2/+2
2026-02-26drm/msm/dpu: fix WD timer handling on DPU 8.xDmitry Baryshkov5-13/+57
2026-02-26drm/msm/dpu: Set vsync source irrespective of mdp top supportTeguh Sobirin1-8/+8
2026-02-26drm/msm/disp/dpu: add merge3d support for sc7280Mahadevan P1-2/+12
2026-02-06drm/msm/a6xx: fix bogus hwcg register updatesJohan Hovold1-2/+0
2026-01-08drm/msm: add PERFCTR_CNTL to ifpc_reglistAnna Maniscalco1-0/+1
2026-01-08drm/msm/dpu: Add missing NULL pointer check for pingpong interfaceNikolay Kuratov1-6/+4
2026-01-08drm/msm/a6xx: Fix out of bound IO access in a6xx_get_gmu_registersAkhil P Oommen1-1/+1
2026-01-02drm/msm/a6xx: move preempt_prepare_postamble after error checkAlok Tiwari1-2/+2
2026-01-02drm/msm: adreno: fix deferencing ifpc_reglist when not declaredNeil Armstrong1-8/+10
2025-12-18drm/msm/a6xx: Improve MX rail fallback in RPMH vote initAkhil P Oommen1-11/+15
2025-12-18drm/msm/a6xx: Fix the gemnoc workaroundAkhil P Oommen1-4/+4
2025-12-18drm/msm/a6xx: Flush LRZ cache before PT switchAkhil P Oommen1-2/+8
2025-12-18drm/msm/a2xx: stop over-complaining about the legacy firmwareDmitry Baryshkov1-1/+1
2025-12-18drm/msm: fix missing NULL check after kcalloc in crashstate_get_bos()Huiwen He1-8/+9
2025-12-18drm/msm: Fix NULL pointer dereference in crashstate_get_vm_logs()Huiwen He1-0/+4
2025-12-18drm/msm/dpu: drop dpu_hw_dsc_destroy() prototypeDmitry Baryshkov1-6/+0
2025-10-31Merge tag 'drm-msm-fixes-2025-10-29' of https://gitlab.freedesktop.org/drm/ms...Simona Vetter14-42/+58
2025-10-29drm/msm/dpu: Fix adjusted mode clock check for 3d mergeJessica Zhang1-0/+3
2025-10-29drm/msm/dpu: Disable broken YUV on QSEED2 hardwareVladimir Lypak1-2/+2
2025-10-29drm/msm/dpu: Require linear modifier for writeback framebuffersVladimir Lypak1-0/+3
2025-10-29drm/msm/dpu: Fix pixel extension sub-samplingVladimir Lypak1-4/+6
2025-10-29drm/msm/dpu: Disable scaling for unsupported scaler typesVladimir Lypak1-1/+1
2025-10-29drm/msm/dpu: Propagate error from dpu_assign_plane_resourcesVladimir Lypak1-1/+1
2025-10-29drm/msm/dpu: Fix allocation of RGB SSPPs without scalingVladimir Lypak1-1/+1
2025-10-29drm/msm: dsi: fix PLL init in bonded modeNeil Armstrong2-17/+2
2025-10-25drm/msm: Ensure vm is created in VM_BIND ioctlRob Clark1-1/+1
2025-10-25drm/msm: Reject MAP_NULL op if no PRRRob Clark3-7/+17
2025-10-16drm/msm: make sure last_fence is always updatedAnna Maniscalco1-4/+5
2025-10-16drm/msm/a6xx: Fix GMU firmware parserAkhil P Oommen1-1/+4
2025-10-16drm/msm: Fix pgtable prealloc error pathRob Clark1-0/+5
2025-10-06drm/msm: Fix GEM free for imported dma-bufsRob Clark1-3/+7
2025-09-16Merge tag 'drm-msm-next-2025-09-12' of https://gitlab.freedesktop.org/drm/msm...Dave Airlie55-880/+1454
2025-09-15Merge tag 'v6.17-rc6' into drm-nextDave Airlie23-192/+280
2025-09-10drm/msm/registers: Sync GPU registers from mesaRob Clark6-475/+508
2025-09-10drm/msm/registers: Generate _HI/LO builders for reg64Rob Clark1-0/+7
2025-09-10drm/msm/registers: Make TPL1_BICUBIC_WEIGHTS_TABLE an arrayRob Clark3-21/+17
2025-09-10drm/msm/registers: Sync gen_header.py from mesaRob Clark1-50/+107
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-05 07:04:22 +0000