summaryrefslogtreecommitdiff
path: root/drivers/pci/controller/dwc
AgeCommit message (Expand)AuthorFilesLines
2021-11-18PCI: uniphier: Serialize INTx masking/unmasking and fix the bit operationKunihiko Hayashi1-16/+10
2021-09-22PCI: tegra194: Fix MSI-X programmingOm Prakash Singh1-1/+1
2021-09-22PCI: tegra194: Fix handling BME_CHGED eventOm Prakash Singh1-15/+15
2021-07-20PCI: tegra194: Fix tegra_pcie_ep_raise_msi_irq() ill-defined shiftJon Hunter1-1/+1
2021-07-20PCI: intel-gw: Fix INTx enableMartin Blumenstingl1-4/+6
2021-05-22PCI: tegra: Fix runtime PM imbalance in pex_ep_event_pex_rst_deassert()Dinghao Liu1-1/+1
2021-05-14PCI: keystone: Let AM65 use the pci_ops defined in pcie-designware-host.cKishon Vijay Abraham I1-1/+2
2021-03-04PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064Ansuel Smith1-1/+3
2020-11-04PCI: dwc: Restore ATU memory resource setup to use last entryRob Herring1-2/+6
2020-10-21Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas1-15/+5
2020-10-21Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas1-0/+13
2020-10-21Merge branch 'remotes/lorenzo/pci/meson'Bjorn Helgaas2-2/+9
2020-10-21Merge branch 'remotes/lorenzo/pci/kirin'Bjorn Helgaas1-1/+5
2020-10-21Merge branch 'remotes/lorenzo/pci/imx6'Bjorn Helgaas1-23/+18
2020-10-20PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus()Hou Zhiqiang1-0/+11
2020-10-13PCI: dwc: Fix MSI page leakage in suspend/resumeJisheng Zhang3-17/+36
2020-10-13PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabledJisheng Zhang1-1/+1
2020-10-13PCI: keystone: Remove iATU register mappingKunihiko Hayashi1-16/+4
2020-10-13PCI: dwc: Add common iATU register supportKunihiko Hayashi1-0/+5
2020-10-05PCI: meson: Build as module by defaultKevin Hilman2-2/+9
2020-09-28PCI: kirin: Return -EPROBE_DEFER in case the gpio isn't readyBean Huo1-1/+5
2020-09-28PCI: dwc: Fix 'cast truncates bits from constant value'Gustavo Pimentel1-1/+1
2020-09-21PCI: layerscape: Add EP mode support for ls1088a and ls2088aXiaowei Bao1-19/+53
2020-09-21PCI: layerscape: Modify the MSIX to the doorbell modeXiaowei Bao1-1/+2
2020-09-21PCI: layerscape: Modify the way of getting capability with different PEXXiaowei Bao1-8/+23
2020-09-21PCI: layerscape: Fix some format issue of the codeXiaowei Bao1-2/+2
2020-09-21PCI: designware-ep: Modify MSI and MSIX CAP way of findingXiaowei Bao2-21/+118
2020-09-21PCI: designware-ep: Move the function of getting MSI capability forwardXiaowei Bao1-4/+4
2020-09-21PCI: designware-ep: Add the doorbell mode of MSI-X in EP modeXiaowei Bao2-0/+31
2020-09-21PCI: designware-ep: Add multiple PFs support for DWCXiaowei Bao3-59/+143
2020-09-10PCI: dwc: Use DBI accessorsRob Herring2-10/+8
2020-09-10PCI: dwc: Move N_FTS setup to common setupRob Herring5-85/+35
2020-09-10PCI: dwc/intel-gw: Drop unused max_widthRob Herring1-4/+0
2020-09-10PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()Rob Herring1-14/+1
2020-09-10PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' propertyRob Herring1-6/+0
2020-09-10PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup codeRob Herring2-4/+1
2020-09-10PCI: dwc: Centralize link gen settingRob Herring11-151/+40
2020-09-08PCI: dwc: Make ATU accessors privateRob Herring2-18/+6
2020-09-08PCI: dwc: Remove read_dbi2 codeRob Herring3-36/+0
2020-09-08PCI: dwc/tegra: Use common Designware port logic register definitionsRob Herring2-34/+28
2020-09-08PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offsetRob Herring3-12/+7
2020-09-08PCI: dwc/qcom: Use common PCI register definitionsRob Herring1-10/+8
2020-09-08PCI: dwc/imx6: Use common PCI register definitionsRob Herring1-23/+14
2020-09-08PCI: dwc/meson: Rework PCI config and DW port logic register accessesRob Herring1-51/+25
2020-09-08PCI: dwc/meson: Drop unnecessary RC config space initializationRob Herring1-20/+0
2020-09-08PCI: dwc/meson: Drop the duplicate number of lanes setupRob Herring1-28/+1
2020-09-08PCI: dwc: Ensure FAST_LINK_MODE is clearedRob Herring2-1/+5
2020-09-08PCI: dwc: Add a 'num_lanes' field to struct dw_pcieRob Herring2-8/+7
2020-09-08PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROLRob Herring1-2/+0
2020-09-08PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()Rob Herring9-34/+11