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path: root/drivers/pci/controller
AgeCommit message (Expand)AuthorFilesLines
2023-05-17PCI: imx6: Install the fault handler only on compatible matchH. Nikolaus Schaller1-0/+7
2022-08-25PCI: tegra194: Fix link up retry sequenceVidya Sagar1-1/+1
2022-08-25PCI: tegra194: Fix Root Port interrupt handlingVidya Sagar1-24/+22
2022-07-29PCI: hv: Fix interrupt mapping for multi-MSIJeffrey Hugo1-8/+53
2022-07-29PCI: hv: Reuse existing IRTE allocation in compose_msi_msg()Jeffrey Hugo1-7/+9
2022-07-29PCI: hv: Fix hv_arch_irq_unmask() for multi-MSIJeffrey Hugo1-2/+4
2022-07-29PCI: hv: Fix multi-MSI to allow more than one MSI vectorJeffrey Hugo1-1/+16
2022-06-14PCI: qcom: Fix unbalanced PHY init on probe errorsJohan Hovold1-1/+3
2022-06-14PCI: qcom: Fix runtime PM imbalance on probe errorsJohan Hovold1-4/+1
2022-06-14PCI: imx6: Fix PERST# start-up sequenceFrancesco Dolcini1-9/+14
2022-06-14PCI: rockchip: Fix find_first_zero_bit() limitDan Carpenter1-2/+1
2022-06-14PCI: cadence: Fix find_first_zero_bit() limitDan Carpenter1-2/+1
2022-05-12PCI: aardvark: Fix reading MSI interrupt numberPali Rohár1-7/+3
2022-05-12PCI: aardvark: Clear all MSIs at setupPali Rohár1-2/+4
2022-04-15PCI: aardvark: Fix support for MSI interruptsPali Rohár1-10/+6
2022-04-15PCI: aardvark: Fix reading PCI_EXP_RTSTA_PME bit on emulated bridgePali Rohár1-1/+3
2022-01-27PCI: pci-bridge-emul: Correctly set PCIe capabilitiesPali Rohár2-1/+11
2021-12-01PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridgePali Rohár1-0/+27
2021-12-01PCI: aardvark: Set PCI Bridge Class Code to PCI BridgePali Rohár1-0/+20
2021-12-01PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridgePali Rohár1-9/+38
2021-12-01PCI: aardvark: Fix link trainingPali Rohár1-83/+34
2021-12-01PCI: aardvark: Simplify initialization of rootcap on virtual bridgePali Rohár1-10/+4
2021-12-01PCI: aardvark: Implement re-issuing config requests on CRS responsePali Rohár1-24/+43
2021-12-01PCI: aardvark: Fix PCIe Max Payload Size settingPali Rohár1-1/+2
2021-12-01PCI: aardvark: Configure PCIe resources from 'ranges' DT propertyPali Rohár1-1/+189
2021-12-01PCI: aardvark: Update comment about disabling link trainingPali Rohár1-1/+8
2021-12-01PCI: aardvark: Move PCIe reset card code to advk_pcie_train_link()Pali Rohár1-30/+34
2021-12-01PCI: aardvark: Fix compilation on s390Pali Rohár1-1/+1
2021-12-01PCI: aardvark: Don't touch PCIe registers if no card connectedPali Rohár1-0/+7
2021-12-01PCI: aardvark: Replace custom macros by standard linux/pci_regs.h macrosPali Rohár1-23/+18
2021-12-01PCI: aardvark: Issue PERST via GPIOPali Rohár1-1/+42
2021-12-01PCI: aardvark: Improve link trainingMarek Behún1-25/+89
2021-12-01PCI: aardvark: Train link immediately after enabling trainingPali Rohár1-6/+9
2021-12-01PCI: aardvark: Fix big endian supportGrzegorz Jaszczyk1-5/+7
2021-12-01PCI: aardvark: Wait for endpoint to be ready before training linkRemi Pommarel1-0/+8
2021-12-01PCI: aardvark: Deduplicate code in advk_pcie_rd_conf()Marek Behún1-28/+20
2021-11-17PCI: aardvark: Fix preserving PCI_EXP_RTCTL_CRSSVE flag on emulated bridgePali Rohár1-0/+1
2021-11-17PCI: aardvark: Don't spam about PIO Response StatusMarek Behún1-1/+1
2021-11-17PCI: aardvark: Read all 16-bits from PCIE_MSI_PAYLOAD_REGMarek Behún1-1/+6
2021-11-17PCI: aardvark: Fix return value of MSI domain .alloc() methodMarek Behún1-1/+1
2021-11-17PCI: aardvark: Fix reporting Data Link Layer Link ActivePali Rohár1-1/+28
2021-11-17PCI: aardvark: Do not unmask unused interruptsPali Rohár1-3/+3
2021-11-17PCI: aardvark: Fix checking for link up via LTSSM statePali Rohár1-6/+70
2021-11-17PCI: aardvark: Do not clear status bits of masked interruptsPali Rohár1-6/+0
2021-09-26PCI: aardvark: Fix reporting CRS valuePali Rohár1-4/+63
2021-09-26PCI: aardvark: Indicate error in 'val' when config read failsPali Rohár1-1/+3
2021-09-22PCI: aardvark: Fix masking and unmasking legacy INTx interruptsPali Rohár1-0/+9
2021-09-22PCI: aardvark: Increase polling delay to 1.5s while waiting for PIO responsePali Rohár1-1/+1
2021-09-22PCI: aardvark: Fix checking for PIO statusEvan Wang1-8/+54
2021-09-22PCI: xilinx-nwl: Enable the clock through CCFHyun Kwon1-0/+12
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