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2023-12-05perf vendor events arm64 AmpereOneX: Add core PMU events and metricsIlkka Koskinen1-0/+1
Add JSON files for AmpereOneX core PMU events and metrics. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20231201021550.1109196-4-ilkka@os.amperecomputing.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2023-09-26perf vendors events: Remove repeated word in commentsCharles Han1-1/+1
Remove the repeated word "of" in comments. Signed-off-by: Charles Han <hanchunchao@inspur.com> Reviewed-by: Ian Rogers <irogers@google.com> Cc: james.clark@arm.com Cc: nick.forrington@arm.com Cc: leo.yan@linaro.org Cc: mike.leach@linaro.org Cc: john.g.garry@oracle.com Cc: ilkka@os.amperecomputing.com Link: https://lore.kernel.org/r/20230918033623.159213-1-hanchunchao@inspur.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
2023-05-15perf vendor events arm64: Add AmpereOne core PMU eventsIlkka Koskinen1-0/+1
Add JSON files for AmpereOne core PMU events. Reviewed-by: John Garry <john.g.garry@oracle.com> Signed-off-by: Doug Rady <dcrady@os.amperecomputing.com> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Acked-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230427223220.1068356-1-ilkka@os.amperecomputing.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2023-03-21perf vendor events arm64: Add N1 metricsJames Clark1-2/+2
Generated from the telemetry solution repo[1] with this command: ./generate.py <linux-repo>/tools/perf/ --telemetry-files \ ../../data/pmu/cpu/neoverse/neoverse-n1.json Since this data source now includes the SPE events for N1, it has diverged from A76 which means the folder has to be split. The new data also uses more fine grained grouping, but this will be consistent for all future products. Long PublicDescriptions are now included even for common events because this can include product specific details. For non verbose mode the common BriefDescriptions remain the same. [1]: https://gitlab.arm.com/telemetry-solution/telemetry-solution Signed-off-by: James Clark <james.clark@arm.com> Acked-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: renyu.zj@linux.alibaba.com Link: https://lore.kernel.org/r/20230320114601.524958-1-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-11-10perf vendor events: Add Arm Neoverse V2 PMU eventsJames Clark1-1/+2
Rename the neoverse-n2 folder to make it clear that it includes V2, and add V2 to mapfile.csv. V2 has the same events as N2, visible by running the following command in the ARM-software/data github repo [1]: diff pmu/neoverse-v2.json pmu/neoverse-n2.json | grep code Testing: $ perf test pmu 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok [1]: https://github.com/ARM-software/data Reviewed-by: Nick Forrington <nick.forrington@arm.com> Signed-off-by: James Clark <james.clark@arm.com> Cc: Al Grant <al.grant@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.garry@huawei.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20221020134512.1345013-1-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-10-04perf vendor events: Update events for Neoverse E1Nick Forrington1-2/+2
These CPUs contain the same PMU events (as per the Arm Technical Reference manuals for Cortex A65 and Neoverse E1) This de-duplicates event data, and avoids issues in previous E1 event data (not present in A65 data) * Missing implementation defined events * Inclusion of events that are not implemented: - L1D_CACHE_ALLOCATE - SAMPLE_POP - SAMPLE_FEED - SAMPLE_FILTRATE - SAMPLE_COLLISION Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220907154932.60808-1-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-07-28perf vendor events arm64: Arm Cortex-A78C and X1CNick Forrington1-0/+2
Add PMU events for the Arm Cortex-A78C and Arm Cortex-X1C CPUs. Events for Arm Cortex-A78C match those for Arm Cortex-A78. Events for Arm Cortex-X1C match those for Arm Cortex- X1. As such, this is just a mapfile change. Main ID Register (MIDR) and event data is sourced from the corresponding Arm Technical Reference Manuals: Arm Cortex-A78C: https://developer.arm.com/documentation/102226/ Arm Cortex-X1C: https://developer.arm.com/documentation/101968/ Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220610174459.615995-1-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Neoverse E1Nick Forrington1-0/+1
Add PMU events for Arm Neoverse E1 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/neoverse-e1.json which is based on PMU event descriptions from the Arm Neoverse E1 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-14-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-X2Nick Forrington1-0/+1
Add PMU events for Arm Cortex-X2 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-x2.json which is based on PMU event descriptions from the Arm Cortex-X2 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-13-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-X1Nick Forrington1-0/+1
Add PMU events for Arm Cortex-X1 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-x1.json which is based on PMU event descriptions from the Arm Cortex-X1 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-12-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-A710Nick Forrington1-0/+1
Add PMU events for Arm Cortex-A710 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a710.json which is based on PMU event descriptions from the Arm Cortex-A710 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-11-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-A78Nick Forrington1-0/+1
Add PMU events for Arm Cortex-A78 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a78.json which is based on PMU event descriptions from the Arm Cortex-A78 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-10-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-A77Nick Forrington1-0/+1
Add PMU events for Arm Cortex-A77 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a77.json which is based on PMU event descriptions from the Arm Cortex-A77 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-9-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-A75Nick Forrington1-0/+1
Add PMU events for Arm Cortex-A75 Add corresponding common events Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a75.json which is based on PMU event descriptions from the Arm Cortex-A75 Technical Reference Manual. Common event data based on: https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json which is based on PMU event descriptions found in the Arm Architecture Reference Manual: https://developer.arm.com/documentation/ddi0487/ Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-8-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-A73Nick Forrington1-0/+1
Add PMU events for Arm Cortex-A73 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a73.json which is based on PMU event descriptions from the Arm Cortex-A73 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-7-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-A65Nick Forrington1-0/+1
Add PMU events for Arm Cortex-A65 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a65.json which is based on PMU event descriptions from the Arm Cortex-A65 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-6-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-A510Nick Forrington1-0/+1
Add PMU events for Arm Cortex-A510 Add corresponding common events Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a510.json which is based on PMU event descriptions from the Arm Cortex-A510 Technical Reference Manual. Common event data based on: https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json which is based on PMU event descriptions found in the Arm Architecture Reference Manual: https://developer.arm.com/documentation/ddi0487/ Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-5-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-A55Nick Forrington1-0/+1
Add PMU events for Arm Cortex-A55 Add corresponding common events Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a55.json which is based on PMU event descriptions from the Arm Cortex-A55 Technical Reference Manual. Common event data based on: https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json which is based on PMU event descriptions found in the Arm Architecture Reference Manual: https://developer.arm.com/documentation/ddi0487/ Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-4-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-A35Nick Forrington1-0/+1
Add PMU events for Arm Cortex-A35 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a35.json which is based on PMU event descriptions from the Arm Cortex-A35 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-3-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-05-23perf vendors events arm64: Arm Cortex-A34Nick Forrington1-0/+1
Add PMU events for Arm Cortex-A34 Add corresponding common events Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a34.json which is based on PMU event descriptions from the Arm Cortex-A34 Technical Reference Manual. Common event data based on: https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json which is based on PMU event descriptions found in the Arm Architecture Reference Manual: https://developer.arm.com/documentation/ddi0487/ Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-2-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2021-12-16perf vendor events: For the Arm Neoverse N2Andrew Kilroy1-0/+1
Updates the common and microarch json file to add counters available in the Arm Neoverse N2 chip, but should also apply to other ArmV8 and ArmV9 cpus. Specified in ArmV8 architecture reference manual https://developer.arm.com/documentation/ddi0487/gb/?lang=en Some of the counters added to armv8-common-and-microarch.json are specified in the ArmV9 architecture reference manual supplement (issue A.a): https://developer.arm.com/documentation/ddi0608/aa The additional ArmV9 counters are TRB_WRAP TRCEXTOUT0 TRCEXTOUT1 TRCEXTOUT2 TRCEXTOUT3 CTI_TRIGOUT4 CTI_TRIGOUT5 CTI_TRIGOUT6 CTI_TRIGOUT7 This patch also adds files in pmu-events/arch/arm64/arm/neoverse-n2 for perf list to output the counter names in categories. Counters on the Neoverse N2 are stated in its reference manual: https://developer.arm.com/documentation/102099/0000 Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20211210123706.7490-2-andrew.kilroy@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2021-10-20perf vendor events arm64: Categorise the Neoverse V1 countersAndrew Kilroy1-0/+1
This is so they are categorised in the perf list output. The pmus all exist in the armv8-common-and-microarch.json and arm-recommended.json files, so this commit places them into each category's own file under tools/perf/pmu-events/arch/arm64/arm/neoverse-v1 Also add the Neoverse V1 to the arm64 mapfile Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20211006081106.8649-3-andrew.kilroy@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2021-03-15perf vendor events arm64: Add Fujitsu A64FX pmu eventShunsuke Nakamura1-0/+1
Add pmu events for A64FX. Documentation source: https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_PMU_Events_v1.2.pdf Signed-off-by: Nakamura, Shunsuke/中村 俊介 <nakamura.shun@fujitsu.com> Reviewed-by: John Garry <john.garry@huawei.com> Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: http://lore.kernel.org/lkml/20210308105342.746940-3-nakamura.shun@fujitsu.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2019-09-20perf tools: Add PMU event JSON files for ARM Cortex-A76 and, Neoverse N1.James Clark1-0/+2
The source of the event codes and description text was the Neoverse N1 technical reference manual at: http://infocenter.arm.com/help/topic/com.arm.doc.100616_0301_01_en/neoverse_n1_trm_100616_0301_01_en.pdf The Cortex-A76 shares the same event IDs as the Neoverse N1 and they can be viewed at: https://static.docs.arm.com/100798/0400/cortex_a76_trm_100798_0400_00_en.pdf Signed-off-by: James Clark <james.clark@arm.com> Cc: "linux-perf-users@vger.kernel.org" <linux-perf-users@vger.kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jeremy Linton <jeremy.linton@arm.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Suzuki Poulouse <suzuki.poulose@arm.com> Cc: james clark <james.clark@arm.com> Cc: nd <nd@arm.com> Link: http://lore.kernel.org/lkml/20190902160713.1425-2-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2019-05-15perf vendor events arm64: Add Cortex-A57 and Cortex-A72 eventsFlorian Fainelli1-0/+2
The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events up to the RC_ST_SPEC (0x91) event with the exception of: - L1D_CACHE_REFILL_INNER (0x44) - L1D_CACHE_REFILL_OUTER (0x45) - L1D_TLB_RD (0x4E) - L1D_TLB_WR (0x4F) - L2D_TLB_REFILL_RD (0x5C) - L2D_TLB_REFILL_WR (0x5D) - L2D_TLB_RD (0x5E) - L2D_TLB_WR (0x5F) - STREX_SPEC (0x6F) Create an appropriate JSON file for mapping those events and update the mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that file. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: John Garry <john.garry@huawei.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sean V Kelley <seanvk.dev@oregontracks.org> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging) Link: http://lkml.kernel.org/r/20190513202522.9050-4-f.fainelli@gmail.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2019-05-15perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 eventsFlorian Fainelli1-0/+1
Broadcom's Brahma-B53 CPUs support the same type of events that the Cortex-A53 supports, recognize its CPUID and map it to the cortex-a53 events. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Will Deacon <will.deacon@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: John Garry <john.garry@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sean V Kelley <seanvk.dev@oregontracks.org> Cc: bcm-kernel-feedback-list@broadcom.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org (moderated list Link: http://lkml.kernel.org/r/20190513202522.9050-3-f.fainelli@gmail.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2019-05-15perf vendor events arm64: Remove [[:xdigit:]] wildcardFlorian Fainelli1-1/+1
ARM64's implementation of get_cpuidr_str() masks out the revision bits [3:0] while reading the CPU identifier, there is no need for the [[:xdigit:]] wildcard. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: John Garry <john.garry@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sean V Kelley <seanvk.dev@oregontracks.org> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging) Link: http://lkml.kernel.org/r/20190513202522.9050-2-f.fainelli@gmail.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2018-08-08perf vendor events arm64: Enable JSON events for eMAGSean V Kelley1-0/+1
This patch adds the Ampere Computing eMAG file. This platform follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable. Signed-off-by: Sean V Kelley <seanvk.dev@oregontracks.org> Reviewed-by: John Garry <john.garry@huawei.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will.deacon@arm.com> Cc: William Cohen <wcohen@redhat.com> Cc: linux-arm-kernel@lists.infradead.org LPU-Reference: 20180803041811.17065-1-seanvk.dev@oregontracks.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2018-03-16perf vendor events arm64: Enable JSON events for ThunderX2 B0Ganapatrao Kulkarni1-0/+1
There is MIDR change on ThunderX2 B0, adding an entry to mapfile to enable JSON events for B0. Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Acked-by: Will Deacon <will.deacon@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ganapatrao Kulkarni <gpkulkarni@gklkml16.com> Cc: Jayachandran C <jnair@caviumnetworks.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: John Garry <john.garry@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Robert Richter <robert.richter@cavium.com> Cc: William Cohen <wcohen@redhat.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20180307110803.32418-1-ganapatrao.kulkarni@cavium.com [ Fixup wrt recent patchset by John Garry ] Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2018-03-16perf vendor events arm64: add HiSilicon hip08 JSON fileJohn Garry1-0/+1
This patch adds the HiSilicon hip08 JSON file. This platform follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable. Signed-off-by: John Garry <john.garry@huawei.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com> Cc: Will Deacon <will.deacon@arm.com> Cc: William Cohen <wcohen@redhat.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-12-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2018-03-16perf vendor events arm64: Relocate Cortex A53 JSONs to arm subdirectoryJohn Garry1-1/+1
Since jevents now supports vendor subdirectory, relocate the Cortex-A53 JSONs to arm subdirectory. Signed-off-by: John Garry <john.garry@huawei.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com> Cc: Will Deacon <will.deacon@arm.com> Cc: William Cohen <wcohen@redhat.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-7-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2018-03-16perf vendor events arm64: Relocate ThunderX2 JSON to cavium subdirectoryJohn Garry1-1/+1
Since jevents now supports vendor subdirectory, relocate the ThunderX2 JSON to Cavium subdirectory. Signed-off-by: John Garry <john.garry@huawei.com> Tested-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com> Cc: Will Deacon <will.deacon@arm.com> Cc: William Cohen <wcohen@redhat.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: http://lkml.kernel.org/r/1520506716-197429-6-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2018-02-15perf vendor events aarch64: Add JSON metrics for ARM Cortex-A53 ProcessorWilliam Cohen1-0/+1
Add JSON metrics for ARM Cortex-A53 Processor. Unlike the Intel processors there isn't a script that automatically generated these files. The patch was manually generated from the documentation and the previous oprofile ARM Cortex ac53 event file patch I made. The relevant documentation is in the "12.9 Events" section of the ARM Cortex A53 MPCore Processor Revision: r0p4 Technical Reference Manual. The ARM Cortex A53 manual is available at: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500g/DDI0500G_cortex_a53_trm.pdf Use that to look for additional information about the events. Signed-off-by: William Cohen <wcohen@redhat.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/20180131032813.9564-1-wcohen@redhat.com [ Added references provided by William Cohen ] Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2017-12-05perf vendor events arm64: Add ThunderX2 implementation defined pmu core eventsGanapatrao Kulkarni1-0/+15
This is not a full event list, but a short list of useful events. Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> Acked-by: Will Deacon <will.deacon@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Ganapatrao Kulkarni <gklkml16@gmail.com> Cc: Jayachandran C <jnair@caviumnetworks.com> Cc: Jonathan Cameron <jonathan.cameron@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Robert Richter <robert.richter@cavium.com> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20171016183222.25750-5-ganapatrao.kulkarni@cavium.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-15 01:30:46 +0000