path: root/arch/arm/mach-omap2/omap_hwmod_81xx_data.c

/*
 * DM81xx hwmod data.
 *
 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/types.h>

#include <linux/platform_data/hsmmc-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <plat/dmtimer.h>

#include "omap_hwmod_common_data.h"
#include "cm81xx.h"
#include "ti81xx.h"
#include "wd_timer.h"

/*
 * DM816X hardware modules integration data
 *
 * Note: This is incomplete and at present, not generated from h/w database.
 */

/*
 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
 */
#define DM81XX_CM_ALWON_MCASP0_CLKCTRL		0x140
#define DM81XX_CM_ALWON_MCASP1_CLKCTRL		0x144
#define DM81XX_CM_ALWON_MCASP2_CLKCTRL		0x148
#define DM81XX_CM_ALWON_MCBSP_CLKCTRL		0x14c
#define DM81XX_CM_ALWON_UART_0_CLKCTRL		0x150
#define DM81XX_CM_ALWON_UART_1_CLKCTRL		0x154
#define DM81XX_CM_ALWON_UART_2_CLKCTRL		0x158
#define DM81XX_CM_ALWON_GPIO_0_CLKCTRL		0x15c
#define DM81XX_CM_ALWON_GPIO_1_CLKCTRL		0x160
#define DM81XX_CM_ALWON_I2C_0_CLKCTRL		0x164
#define DM81XX_CM_ALWON_I2C_1_CLKCTRL		0x168
#define DM81XX_CM_ALWON_WDTIMER_CLKCTRL		0x18c
#define DM81XX_CM_ALWON_SPI_CLKCTRL		0x190
#define DM81XX_CM_ALWON_MAILBOX_CLKCTRL		0x194
#define DM81XX_CM_ALWON_SPINBOX_CLKCTRL		0x198
#define DM81XX_CM_ALWON_MMUDATA_CLKCTRL		0x19c
#define DM81XX_CM_ALWON_MMUCFG_CLKCTRL		0x1a8
#define DM81XX_CM_ALWON_CONTROL_CLKCTRL		0x1c4
#define DM81XX_CM_ALWON_GPMC_CLKCTRL		0x1d0
#define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL	0x1d4
#define DM81XX_CM_ALWON_L3_CLKCTRL		0x1e4
#define DM81XX_CM_ALWON_L4HS_CLKCTRL		0x1e8
#define DM81XX_CM_ALWON_L4LS_CLKCTRL		0x1ec
#define DM81XX_CM_ALWON_RTC_CLKCTRL		0x1f0
#define DM81XX_CM_ALWON_TPCC_CLKCTRL		0x1f4
#define DM81XX_CM_ALWON_TPTC0_CLKCTRL		0x1f8
#define DM81XX_CM_ALWON_TPTC1_CLKCTRL		0x1fc
#define DM81XX_CM_ALWON_TPTC2_CLKCTRL		0x200
#define DM81XX_CM_ALWON_TPTC3_CLKCTRL		0x204

/* Registers specific to dm814x */
#define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL	0x16c
#define DM814X_CM_ALWON_ATL_CLKCTRL		0x170
#define DM814X_CM_ALWON_MLB_CLKCTRL		0x174
#define DM814X_CM_ALWON_PATA_CLKCTRL		0x1