path: root/arch/arm64/Kconfig

config ARM64
	def_bool y
	select ACPI_CCA_REQUIRED if ACPI
	select ACPI_GENERIC_GSI if ACPI
	select ACPI_GTDT if ACPI
	select ACPI_IORT if ACPI
	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
	select ACPI_MCFG if ACPI
	select ACPI_SPCR_TABLE if ACPI
	select ARCH_CLOCKSOURCE_DATA
	select ARCH_HAS_DEBUG_VIRTUAL
	select ARCH_HAS_DEVMEM_IS_ALLOWED
	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
	select ARCH_HAS_ELF_RANDOMIZE
	select ARCH_HAS_FORTIFY_SOURCE
	select ARCH_HAS_GCOV_PROFILE_ALL
	select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
	select ARCH_HAS_KCOV
	select ARCH_HAS_SET_MEMORY
	select ARCH_HAS_SG_CHAIN
	select ARCH_HAS_STRICT_KERNEL_RWX
	select ARCH_HAS_STRICT_MODULE_RWX
	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
	select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
	select ARCH_INLINE_READ_LOCK if !PREEMPT
	select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
	select ARCH_INLINE_READ_UNLOCK if !PREEMPT
	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
	select ARCH_INLINE_WRITE_LOCK if !PREEMPT
	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
	select ARCH_USE_CMPXCHG_LOCKREF
	select ARCH_USE_QUEUED_RWLOCKS
	select ARCH_SUPPORTS_MEMORY_FAILURE
	select ARCH_SUPPORTS_ATOMIC_RMW
	select ARCH_SUPPORTS_NUMA_BALANCING
	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
	select ARCH_WANT_FRAME_POINTERS
	select ARCH_HAS_UBSAN_SANITIZE_ALL
	select ARM_AMBA
	select ARM_ARCH_TIMER
	select ARM_GIC
	select AUDIT_ARCH_COMPAT_GENERIC
	select ARM_GIC_V2M if PCI
	select ARM_GIC_V3
	select ARM_GIC_V3_ITS if PCI
	select ARM_PSCI_FW
	select BUILDTIME_EXTABLE_SORT
	select CLONE_BACKWARDS
	select COMMON_CLK
	select CPU_PM if (SUSPEND || CPU_IDLE)
	select DCACHE_WORD_ACCESS
	select EDAC_SUPPORT
	select FRAME_POINTER
	select GENERIC_ALLOCATOR
	select GENERIC_ARCH_TOPOLOGY
	select GENERIC_CLOCKEVENTS
	select GENERIC_CLOCKEVENTS_BROADCAST
	select GENERIC_CPU_AUTOPROBE
	select GENERIC_EARLY_IOREMAP
	select GENERIC_IDLE_POLL_SETUP
	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
	select GENERIC_IRQ_SHOW_LEVEL
	select GENERIC_PCI_IOMAP
	select GENERIC_SCHED_CLOCK
	select GENERIC_SMP_IDLE_THREAD
	select GENERIC_STRNCPY_FROM_USER
	select GENERIC_STRNLEN_USER
	select GENERIC_TIME_VSYSCALL
	select HANDLE_DOMAIN_IRQ
	select HARDIRQS_SW_RESEND
	select HAVE_ACPI_APEI if (ACPI && EFI)
	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
	select HAVE_ARCH_AUDITSYSCALL
	select HAVE_ARCH_BITREVERSE
	select HAVE_ARCH_HUGE_VMAP
	select HAVE_ARCH_JUMP_LABEL
	select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
	select HAVE_ARCH_KGDB
	select HAVE_ARCH_MMAP_RND_BITS
	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
	select HAVE_ARCH_SECCOMP_FILTER
	select HAVE_ARCH_TRACEHOOK
	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
	select HAVE_ARCH_VMAP_STACK
	select HAVE_ARM_SMCCC
	select HAVE_EBPF_JIT
	select HAVE_C_RECORDMCOUNT
	select HAVE_CC_STACKPROTECTOR
	select HAVE_CMPXCHG_DOUBLE
	select HAVE_CMPXCHG_LOCAL
	select HAVE_CONTEXT_TRACKING
	select HAVE_DEBUG_BUGVERBOSE
	select HAVE_DEBUG_KMEMLEAK
	select HAVE_DMA_API_DEBUG
	select HAVE_DMA_CONTIGUOUS
	select HAVE_DYNAMIC_FTRACE
	select HAVE_EFFICIENT_UNALIGNED_ACCESS
	select HAVE_FTRACE_MCOUNT_RECORD
	select HAVE_FUNCTION_TRACER
	select HAVE_FUNCTION_GRAPH_TRACER
	select HAVE_GCC_PLUGINS
	select HAVE_GENERIC_DMA_COHERENT
	select HAVE_HW_BREAKPOINT if PERF_EVENTS
	select HAVE_IRQ_TIME_ACCOUNTING
	select HAVE_MEMBLOCK
	select HAVE_MEMBLOCK_NODE_MAP if NUMA
	select HAVE_NMI if ACPI_APEI_SEA
	select HAVE_PATA_PLATFORM
	select HAVE_PERF_EVENTS
	select HAVE_PERF_REGS
	select HAVE_PERF_USER_STACK_DUMP
	select HAVE_REGS_AND_STACK_ACCESS_API
	select HAVE_RCU_TABLE_FREE
	select HAVE_SYSCALL_TRACEPOINTS
	select HAVE_KPROBES
	select HAVE_KRETPROBES
	select IOMMU_DMA if IOMMU_SUPPORT
	select IRQ_DOMAIN
	select IRQ_FORCED_THREADING
	select MODULES_USE_ELF_RELA
	select NO_BOOTMEM
	select OF
	select OF_EARLY_FLATTREE
	select OF_RESERVED_MEM
	select PCI_ECAM if ACPI
	select POWER_RESET
	select POWER_SUPPLY
	select SPARSE_IRQ
	select SYSCTL_EXCEPTION_TRACE
	select THREAD_INFO_IN_TASK
	help
	  ARM 64-bit (AArch64) Linux support.

config 64BIT
	def_bool y

config ARCH_PHYS_ADDR_T_64BIT
	def_bool y

config MMU
	def_bool y

config ARM64_PAGE_SHIFT
	int
	default 16 if ARM64_64K_PAGES
	default 14 if ARM64_16K_PAGES
	default 12

config ARM64_CONT_SHIFT
	int
	default 5 if ARM64_64K_PAGES
	default 7 if ARM64_16K_PAGES
	default 4

config ARCH_MMAP_RND_BITS_MIN
       default 14 if ARM64_64K_PAGES
       default 16 if ARM64_16K_PAGES
       default 18

# max bits determined by the following formula:
#  VA_BITS - PAGE_SHIFT - 3
config ARCH_MMAP_RND_BITS_MAX
       default 19 if ARM64_VA_BITS=36
       default 24 if ARM64_VA_BITS=39
       default 27 if ARM64_VA_BITS=42
       default 30 if ARM64_VA_BITS=47
       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
       default 33 if ARM64_VA_BITS=48
       default 14 if ARM64_64K_PAGES
       default 16 if ARM64_16K_PAGES
       default 18

config ARCH_MMAP_RND_COMPAT_BITS_MIN
       default 7 if ARM64_64K_PAGES
       default 9 if ARM64_16K_PAGES
       default 11

config ARCH_MMAP_RND_COMPAT_BITS_MAX
       default 16

config NO_IOPORT_MAP
	def_bool y if !PCI

config STACKTRACE_SUPPORT
	def_bool y

config ILLEGAL_POINTER_VALUE
	hex
	default 0xdead000000000000

config LOCKDEP_SUPPORT
	def_bool y

config TRACE_IRQFLAGS_SUPPORT
	def_bool y

config RWSEM_XCHGADD_ALGORITHM
	def_bool y

config GENERIC_BUG
	def_bool y
	depends on BUG

config GENERIC_BUG_RELATIVE_POINTERS
	def_bool y
	depends on GENERIC_BUG

config GENERIC_HWEIGHT
	def_bool y

config GENERIC_CSUM
        def_bool y

config GENERIC_CALIBRATE_DELAY
	def_bool y

config ZONE_DMA
	def_bool y

config HAVE_GENERIC_GUP
	def_bool y

config ARCH_DMA_ADDR_T_64BIT
	def_bool y

config NEED_DMA_MAP_STATE
	def_bool y

config NEED_SG_DMA_LENGTH
	def_bool y

config SMP
	def_bool y

config SWIOTLB
	def_bool y

config IOMMU_HELPER
	def_bool SWIOTLB

config KERNEL_MODE_NEON
	def_bool y

config FIX_EARLYCON_MEM
	def_bool y

config PGTABLE_LEVELS
	int
	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48

config ARCH_SUPPORTS_UPROBES
	def_bool y

config ARCH_PROC_KCORE_TEXT
	def_bool y

source "init/Kconfig"

source "kernel/Kconfig.freezer"

source "arch/arm64/Kconfig.platforms"

menu "Bus support"

config PCI
	bool "PCI support"
	help
	  This feature enables support for PCI bus system. If you say Y
	  here, the kernel will include drivers and infrastructure code
	  to support PCI bus devices.

config PCI_DOMAINS
	def_bool PCI

config PCI_DOMAINS_GENERIC
	def_bool PCI

config PCI_SYSCALL
	def_bool PCI

source "drivers/pci/Kconfig"

endmenu

menu "Kernel Features"

menu "ARM errata workarounds via the alternatives framework"

config ARM64_ERRATUM_826319
	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
	  AXI master interface and an L2 cache.

	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
	  and is unable to accept a certain write via this interface, it will
	  not progress on read data presented on the read data channel and the
	  system can deadlock.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_827319
	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
	  master interface and an L2 cache.

	  Under certain conditions this erratum can cause a clean line eviction
	  to occur at the same time as another transaction to the same address
	  on the AMBA 5 CHI interface, which can cause data corruption if the
	  interconnect reorders the two transactions.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_824069
	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
	  to a coherent interconnect.

	  If a Cortex-A53 processor is executing a store or prefetch for
	  write instruction at the same time as a processor in another
	  cluster is executing a cache maintenance operation to the same
	  address, then this erratum might cause a clean cache line to be
	  incorrectly marked as dirty.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this option does not necessarily enable the
	  workaround, as it depends on the alternative framework, which will
	  only patch the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_819472
	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
	  present when it is connected to a coherent interconnect.

	  If the processor is executing a load and store exclusive sequence at
	  the same time as a processor in another cluster is executing a cache
	  maintenance operation to the same address, then this erratum might
	  cause data corruption.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_832075
	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 832075 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might deadlock when exclusive load/store
	  instructions to Write-Back memory are mixed with Device loads.

	  The workaround is to promote device loads to use Load-Acquire
	  semantics.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_834220
	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
	depends on KVM
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 834220 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might report a Stage 2 translation
	  fault as the result of a Stage 1 fault for load crossing a
	  page boundary when there is a permission or device memory
	  alignment fault at Stage 1 and a translation fault at Stage 2.

	  The workaround is to verify that the Stage 1 translation
	  doesn't generate a fault before handling the Stage 2 fault.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_845719
	bool "Cortex-A53: 845719: a load might read incorrect data"
	depends on COMPAT
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 845719 on Cortex-A53 parts up to r0p4.

	  When running a compat (AArch32) userspace on an affected Cortex-A53
	  part, a load at EL0 from a virtual address that matches the bottom 32
	  bits of the virtual address used by a recent load at (AArch64) EL1
	  might return incorrect data.

	  The workaround is to write the contextidr_el1 register on exception
	  return to a 32-bit task.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_843419
	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
	default y
	select ARM64_MODULE_CMODEL_LARGE if MODULES
	help
	  This option links the kernel with '--fix-cortex-a53-843419' and
	  builds modules using the large memory model in order to avoid the use
	  of the ADRP instruction, which can cause a subsequent memory access
	  to use an incorrect address on Cortex-A53 parts up to r0p4.

	  If unsure, say Y.

config CAVIUM_ERRATUM_22375
	bool "Cavium erratum 22375, 24313"
	default y
	help
	  Enable workaround for erratum 22375, 24313.

	  This implements two gicv3-its errata workarounds for ThunderX. Both
	  with small impact affecting only ITS table allocation.

	    erratum 22375: only alloc 8MB table size
	    erratum 24313: ignore memory access type

	  The fixes are in ITS initialization and basically ignore memory access
	  type and table size provided by the TYPER and BASER registers.

	  If unsure, say Y.

config CAVIUM_ERRATUM_23144
	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
	depends on NUMA
	default y
	help
	  ITS SYNC command hang for cross node io and collections/cpu mapping.

	  If unsure, say Y.

config CAVIUM_ERRATUM_23154
	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
	default y
	help
	  The gicv3 of ThunderX requires a modified version for
	  reading the IAR status to ensure data synchronization
	  (access to icc_iar1_el1 is not sync'ed before and after).

	  If unsure, say Y.

config CAVIUM_ERRATUM_27456
	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
	default y
	help
	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
	  instructions may cause the icache to become corrupted if it
	  contains data for a non-current ASID.  The fix is to
	  invalidate the icache when changing the mm context.

	  If unsure, say Y.

config CAVIUM_ERRATUM_30115
	bool "Cavium erratum 30115: Guest may disable interrupts in host"
	default y
	help
	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
	  1.2, and T83 Pass 1.0, KVM guest execution may disable
	  interrupts in host. Trapping both GICv3 group-0 and group-1
	  accesses sidesteps the issue.

	  If unsure, say Y.

config QCOM_FALKOR_ERRATUM_1003
	bool "Falkor E1003: Incorrect translation due to ASID change"
	default y
	select ARM64_PAN if ARM64_SW_TTBR0_PAN
	help
	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
	  and BADDR are changed together in TTBRx_EL1. The workaround for this
	  issue is to use a reserved ASID in cpu_do_switch_mm() before
	  switching to the new ASID. Saying Y here selects ARM64_PAN if
	  ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
	  maintaining the E1003 workaround in the software PAN emulation code
	  would be an unnecessary complication. The affected Falkor v1 CPU
	  implements ARMv8.1 hardware PAN support and using hardware PAN
	  support versus software PAN emulation is mutually exclusive at
	  runtime.

	  If unsure, say Y.

config QCOM_FALKOR_ERRATUM_1009
	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
	default y
	help
	  On Falkor v1, the CPU may prematurely complete a DSB following a
	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
	  one more time to fix the issue.

	  If unsure, say Y.

config QCOM_QDF2400_ERRATUM_0065
	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
	default y
	help
	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).

	  If unsure, say Y.

endmenu


choice
	prompt "Page size"
	default ARM64_4K_PAGES
	help
	  Page size (translation granule) configuration.

config ARM64_4K_PAGES
	bool "4KB"
	help
	  This feature enables 4KB pages support.

config ARM64_16K_PAGES
	bool "16KB"
	help
	  The system will use 16KB pages support. AArch32 emulation
	  requires applications compiled with 16K (or a multiple of 16K)
	  aligned segments.

config ARM64_64K_PAGES
	bool "64KB"
	help
	  This feature enables 64KB pages support (4KB by default)
	  allowing only two levels of page tables and faster TLB
	  look-up. AArch32 emulation requires applications compiled
	  with 64K aligned segments.

endchoice

choice
	prompt "Virtual address space size"
	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
	help
	  Allows choosing one of multiple possible virtual address
	  space sizes. The level of translation table is determined by
	  a combination of page size and virtual address space size.

config ARM64_VA_BITS_36
	bool "36-bit" if EXPERT
	depends on ARM64_16K_PAGES

config ARM64_VA_BITS_39
	bool "39-bit"
	depends on ARM64_4K_PAGES

config ARM64_VA_BITS_42
	bool "42-bit"
	depends on ARM64_64K_PAGES

config ARM64_VA_BITS_47
	bool "47-bit"
	depends on ARM64_16K_PAGES

config ARM64_VA_BITS_48
	bool "48-bit"

endchoice

config ARM64_VA_BITS
	int
	default 36 if ARM64_VA_BITS_36
	default 39 if ARM64_VA_BITS_39
	default 42 if ARM64_VA_BITS_42
	default 47 if ARM64_VA_BITS_47
	default 48 if ARM64_VA_BITS_48

config CPU_BIG_ENDIAN
       bool "Build big-endian kernel"
       help
         Say Y if you plan on running a kernel in big-endian mode.

config SCHED_MC
	bool "Multi-core scheduler support"
	help
	  Multi-core scheduler support improves the CPU scheduler's decision
	  making when dealing with multi-core CPU chips at a cost of slightly
	  increased overhead in some places. If unsure say N here.

config SCHED_SMT
	bool "SMT scheduler support"
	help
	  Improves the CPU scheduler's decision making when dealing with
	  MultiThreading at a cost of slightly increased overhead in some
	  places. If unsure say N here.

config NR_CPUS
	int "Maximum number of CPUs (2-4096)"
	range 2 4096
	# These have to remain sorted largest to smallest
	default "64"

config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
	select GENERIC_IRQ_MIGRATION
	help
	  Say Y here to experiment with turning CPUs off and on.  CPUs
	  can be controlled through /sys/devices/system/cpu.

# Common NUMA Features
config NUMA
	bool "Numa Memory Allocation and Scheduler Support"
	select ACPI_NUMA if ACPI
	select OF_NUMA
	help
	  Enable NUMA (Non Uniform Memory Access) support.

	  The kernel will try to allocate memory used by a CPU on the
	  local memory of the CPU and add some more
	  NUMA awareness to the kernel.

config NODES_SHIFT
	int "Maximum NUMA Nodes (as a power of 2)"
	range 1 10
	default "2"
	depends on NEED_MULTIPLE_NODES
	help
	  Specify the maximum number of NUMA Nodes available on the target
	  system.  Increases memory reserved to accommodate various tables.

config USE_PERCPU_NU